Principal Digital Design Engineer (ASIC)

Analog Devices•Wilmington, MA

1d•$159,638 - $239,457•Onsite

About The Position

As a Principal Digital Design Engineer, you will drive technical strategy and innovation for complex digital systems, including System on Chips (SoCs). You'll define product and technology roadmaps, lead ASIC architecture for mission-critical projects, and serve as a technical authority within the organization. This position requires exceptional expertise across multiple domains and the ability to influence business direction while mentoring and developing technical talent.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of experience in digital design for ASIC/SoC, with track record of successful tapeouts.
Strong understanding of ASIC Design flow
Expertise in RTL design (SystemVerilog), logic synthesis, and digital verification methodologies with Cadence tools.
Experience with modeling and scripting (Matlab, TCL, Python) for design automation.
Strong understanding of digital design flows, timing analysis, and constraints.
Experience collaborating across functions (DV, PD, systems, analog/mixed-signal).
Excellent communication and documentation skills.
Demonstrated ability to lead technical projects or major design subsystems.
Strong understanding of business context and ability to align technical strategy with business goals

Nice To Haves

Experience with high-speed interfaces, high speed signal processing, and low-power design.
Familiarity with UVM or similar verification frameworks.
Prior mentorship or technical leadership experience.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience
12+ years of relevant experience in digital design engineering

Responsibilities

Develop and maintain system-level models (e.g., in SystemVerilog, or MATLAB) to analyze architectural trade-offs, verify system behavior, and inform hardware/software partitioning.
Own the architecture, micro-architecture, and RTL design of complex digital blocks and/or subsystems (such as signal processing functions, control, or processor subsystems) for mixed signal ICs.
Collaborate closely with multi location teams such as system architects, analog designers, DV, physical design, product engineering, applications, and firmware teams to during architecture, design, evaluation, and release phases.
Lead design reviews, participate in specification, and ensure alignment with broader project goals.
Perform RTL coding (Verilog and SystemVerilog), synthesis, and lint/CDC analysis; drive designs to timing closure and area/power targets.
Develop and execute verification plans in collaboration with DV, including functional coverage and support for simulation/debug.
Analyze and resolve design, timing, and functional issues across the full digital development flow.
Contribute to top-level integration, including interface definition, constraint development, and support for physical implementation for functional and DFT modes.
Mentor and guide junior engineers, sharing expertise and promoting best practices.
Author and maintain clear documentation, user guides, and design collateral.
Stay current with industry trends and identify opportunities for process or technology improvement.
Perform silicon lab evaluation and debug.
Use Python applications to develop tests on evaluation platforms.