Principal ASIC Design Engineer

Credo•Ottawa, ON

About The Position

As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, and STA teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation. Credo's mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI. Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world.

Requirements

BS/MS degree in Electrical Engineering or Computer Science.
10+ years of relevant ASIC design experience.
Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
Proficiency in Verilog/SystemVerilog RTL design.
Experience in high-speed Serdes design and familiar with Ethernet (802.3) standards.
Knowledge of synthesis and static timing analysis.
Experience developing testbenches and test cases; familiarity with UVM.
Experience with gate-level simulations, chip bring-up, and validation.
Proven track record of successful production tape-outs.

Nice To Haves

Expertise in scripting languages (Python, Tcl, Perl, Shell).
Familiarity with DFT methodology and physical design flow.
Knowledge of UCIE, or UAlink, AXI/CHI interface is a plus.
Hands-on experience with STA and timing closure.
Strong problem-solving and planning skills.
Excellent communication and collaboration abilities.

Responsibilities

Design, implement, and debug complex logic blocks.
Integrate complex IPs from internal and external vendors.
Support front-end integration activities such as Lint, CDC, synthesis, and ECO.
Participate in design and code reviews to ensure quality.
Develop functional tests/testbenches and run RTL and gate-level simulations.
Work with verification, DFT, and physical design engineers to achieve successful tape-outs.
Bring up, validate, and debug chip features; collaborate with software, firmware, and systems teams.