Principal DFT Engineer
About The Position
MaxLinear is seeking a Principal DFT (Design For Test) Engineer to join our team. In this role, you will focus on leading DFT and implementation of DFT techniques on System on Chip (SOC). You will define DFT architecture, RTL coding, simulation and verification, chip testing, and supporting Automatic Test Equipment (ATE) issues. Additionally, you will develop DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies. You will also generate DFT pattern, coverage analysis, and debug, as well as run and debug gate level simulations. Assisting Test Engineers to bring up ATPG and MBIST pattern on the ATE and resolving issues during characterization are also key aspects of this role.
Requirements
- Strong understanding of Fault modeling, Scan compression, and Memory testing techniques
- Experience in all aspects of DFT flow, including DC/AC scan, ATPG, JTAG/boundary SCAN, memory BIST, high speed interface test
- Understanding of the entire ASIC design flow: logic design, Verilog/VHDL verification, synthesis, timing, and backend
- Proven record of supporting a large volume of commercial SOC shipments
- Excellent analytical and debugging skills and the ability to proactively resolve issues
- Must be able to work autonomously and guide others based on changing priorities
- Proven ability to thrive on, learn, and adapt to new methodologies and technologies
- Excellent oral and written communication skills
- BS in Electrical Engineering or related + 9 years of experience, or MS + 7 years of experience, or Ph.D. + 4 years of experience
Responsibilities
- Lead DFT and implementation of DFT techniques on System on Chip (SOC)
- Define DFT architecture, RTL coding, simulation and verification, chip testing, and supporting Automatic Test Equipment (ATE) issues
- Develop DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies
- Generate DFT pattern, coverage analysis, and debug as well as running and debugging gate level simulations
- Assist Test Engineers to bring up ATPG and MBIST pattern on the ATE
- Resolve issues during characterization
Benefits
- health care benefits
- 401k savings plan
- Employee Stock Purchase Plan (ESPP)
- paid time off
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What This Job Offers
Job Type
Full-time
Career Level
Principal
Education Level
Ph.D. or professional degree
Number of Employees
501-1,000 employees
