Principal DFT Engineer

MaxLinear, Inc. • Carlsbad, CA

4h • Onsite

About The Position

MaxLinear is seeking a Principal DFT (Design For Test) Engineer to join their team. The company is a global, NASDAQ-traded fabless system-on-chip product company focused on improving communication networks through highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. MaxLinear has a history of innovation, including developing the world’s first high-performance TV tuner chip using standard CMOS process technology. They have expanded through organic growth and acquisitions, such as Intel’s Home Gateway Platform Division, to deliver complete end-to-end solutions. The company has approximately 1,200 employees, a substantial majority of whom have engineering degrees, and fosters innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. In this role, the Principal DFT Engineer will lead DFT and implementation of DFT techniques on System on Chip (SOC), define DFT architecture, RTL coding, simulation and verification, chip testing, and support Automatic Test Equipment (ATE) issues. They will also develop DFT methodologies to reduce test cost, increase product quality, and enhance yield learning on leading-edge process technologies, generate DFT patterns, perform coverage analysis and debug, and run/debug gate-level simulations. The engineer will assist Test Engineers with ATPG and MBIST pattern bring-up on the ATE and resolve issues during characterization.

Requirements

• Strong understanding of Fault modeling, Scan compression, and Memory testing techniques
• Experience in all aspects of DFT flow, including DC/AC scan, ATPG, JTAG/boundary SCAN, memory BIST, high speed interface test
• Understanding of the entire ASIC design flow: logic design, Verilog/VHDL verification, synthesis, timing, and backend
• Proven record of supporting a large volume of commercial SOC shipments
• Excellent analytical and debugging skills and the ability to proactively resolve issues
• Must be able to work autonomously and guide others based on changing priorities
• Proven ability to thrive on, learn, and adapt to new methodologies and technologies
• Excellent oral and written communication skills
• BS in Electrical Engineering or related + 9 years of experience, or MS + 7 years of experience, or Ph.D. + 4 years of experience

Responsibilities

• Lead DFT and implementation of DFT techniques on System on Chip (SOC)
• Define DFT architecture, RTL coding, simulation and verification, chip testing, and supporting Automatic Test Equipment (ATE) issues
• Develop DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies
• Generate DFT pattern, coverage analysis, and debug as well as running and debugging gate level simulations
• Assist Test Engineers to bring up ATPG and MBIST pattern on the ATE
• Resolve issues during characterization

Benefits

• base salary
• annual discretionary bonus eligibility
• stock-based compensation
• competitive benefits designed to support employee health, welfare, and retirement
• health care benefits
• 401k savings plan
• Employee Stock Purchase Plan (ESPP)
• paid time off

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 501-1,000 employees