Principal Design Verification Engineer - QGOV

Qualcomm•San Diego, CA

1d•Onsite

About The Position

This role is for a Principal Design Verification Engineer in the QGOV sector. The engineer will be responsible for developing verification methodologies, ensuring scalable and portable environments across simulation and emulation. They will develop test plans to verify hardware building blocks, design macros, and standard interfaces like PCIE, DDR, USB, I2C, and SPI. The role involves owning end-to-end DV tasks, including coding test benches and test cases, writing assertions, running simulations, and achieving coverage goals. The engineer will also explore innovative DV methodologies (formal, simulation, and emulation-based) to enhance test bench quality and efficiency. Additionally, they will develop and maintain the emulation environment and collect relevant metrics. The position requires the candidate to be in San Diego full-time, 5 days a week. Applicants will undergo a government security investigation and must meet eligibility requirements for access to classified information, including being a U.S. citizen eligible for a U.S. Government security clearance.

Requirements

10+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture
10+ years of Design Verification, Emulation and Debug experience with simulation and emulation and prototyping flows
Relevant experience of 10+ yrs in any of the mentioned domain - Design/Verification/ Implementation
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Must be a U.S. citizen and eligible to receive a U.S. Government security clearance
Must be in San Diego full time, 5 days a week

Nice To Haves

Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.
Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
Good understanding of chip-level functional model building
Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C
Knowledge of Behavioral and Structural models and familiarity with simulation environments
Experience customizing and debugging make-based build flows and working with Xilinx’s Vivado tools
Experience with cm tools such as Git and Gerrit.
Experience in formal / static verification methodologies will be a plus
Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.
Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.
Experience with C/C++ DPI transactors and monitors.
Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc.
Experience with GLS, and scripting languages such as Perl, Python is a plus
Linux OS proficiency
Self-starter with strong initiative, discipline, motivation, and a focus on quality.
Team player and be flexible and open to a variety of task assignments within the team.

Responsibilities

Develop verification methodology, ensuring scalable and portable environment across simulation and emulation.
Develop test plan to verify Hardware building blocks, Design macros and Standard interfaces (PCIE, DDR, USB, I2C, SPI, etc).
Own end to end DV tasks from coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals
Explore innovative DV methodologies (formal, simulation and emulation based) to continuously push the quality and efficiency of test benches
Develop and maintain emulation environment to collect metrics related to emulation environment.
Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors.
Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations.
Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.