Principal Design Verification Engineer

Bolt Graphics•Sunnyvale, CA

1d•$250,000 - $280,000

About The Position

As a Principal Design Verification Engineer, you will own the verification strategy and execution for complex IPs or full-chip SoC. You will lead a team of verification engineers, define methodologies, drive coverage closure, and ensure high-quality silicon delivery.

Requirements

Bachelor’s/Master’s degree in Electrical Engineering or related field
12–15 years of experience in ASIC/SoC design verification
Proven experience leading verification teams and delivering multiple tapeouts
Strong expertise in: SystemVerilog and UVM methodology Functional coverage, assertions (SVA), and constrained-random verification Debugging complex SoC-level issues
Hands-on experience with industry-standard tools such as: Synopsys VCS / Cadence Xcelium Synopsys Verdi
Strong understanding of: Clock/reset domain crossings (CDC/RDC) Low-power verification methodologies Gate-level simulation and SDF annotation
Excellent leadership, communication, and problem-solving skills

Nice To Haves

Experience in CPU/GPU/AI/Networking SoCs
Expertise in GLS debug (X-propagation, SDF issues, timing failures)
Familiarity with emulation platforms (e.g., Synopsys ZeBu)
Experience with post-silicon validation and bring-up
Knowledge of performance verification and system-level validation
Strong scripting skills (Python/TCL) for automation and regression scaling

Responsibilities

Define and drive end-to-end verification strategy (block → subsystem → full-chip)
Build, mentor, and scale a high-performing DV team
Establish verification plans, milestones, and coverage goals
Drive alignment across architecture, RTL, and physical design teams
Lead development of UVM-based verification environments
Define testbench architecture, stimulus strategy, and reusable components
Drive functional, code, and assertion coverage closure
Oversee regression infrastructure, debug, and signoff criteria
Drive GLS (Gate-Level Simulation) with SDF annotation and timing-aware debug
Manage low-power verification (UPF/CPF) and power-aware simulation
Oversee formal verification, linting, CDC/RDC analysis
Ensure robust reset, clocking, and cross-domain verification
Work with RTL teams on design-for-verification (DFV) improvements
Collaborate with PD teams on timing-related verification issues
Support post-silicon bring-up and debug
Interface with customers/partners on verification readiness and quality