Principal Design Engineer

Cadence Systems • San Jose, CA

2d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Requirements

• BS degree in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum 1 years of experience.
• Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus.
• Experience with advanced technologies like 5nm, 3ns and 2nm nodes.
• Experience using Linux servers, Script development using Shell/Perl/TCL.
• Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.

Responsibilities

• Implement, verify, timing closure to tape out Palladium and Protium SOCs.
• Lead a team to implement SOCs or sub system chips.
• Work on RTL synthesis and floor planning.
• Build clock trees and perform optimizations.
• Close timing, IR drop and physical verification.
• Review and Document designs for taping out.
• Interface with Front End RTL design teams and Back End Verification teams.

Benefits

• paid vacation
• paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options

What This Job Offers

• Job Type: Full-time
• Career Level: Principal