Principal Analog Layout Design Engineer/Lead

Celero Communications • San Jose, CA

17h

About The Position

Celero Communication Inc. is seeking a Principal/Senior Analog Layout Engineer to drive layout design for complex analog and mixed-signal IP blocks used in advanced optical communication systems. As a member of the Analog & Mixed-Signal design team, this hands-on technical role leads layout development for critical blocks such as ADCs, DACs, and PLLs, working closely with circuit designers, CAD/PDK teams, and other layout engineers to support first-pass silicon success. The role also includes mentoring junior engineers and contributing to chip development in a fast-paced startup environment.

Requirements

• At least 10 years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
• Proven track record integrating top-level IP layout macros and preparing IP for handoff to Physical Design.
• Proven leadership owning major IP layout macros or full-chip-level layout at FinFET nodes; TSMC experience is preferred.
• At least 1 year of experience with TSMC FinFET process nodes N3, N5, N7, or N16.
• Deep understanding of device physics and layout-dependent effects, including LOD, WPE, OSE, and LDE, and their impact on circuit performance.
• Strong expertise in layout practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization.
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design.
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools.
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules.
• Experience working collaboratively with international and remote teams.
• Strong documentation and communication skills, including the ability to present layout trade-offs and status to cross-functional teams.
• Experience using revision control systems for layout design management.

Nice To Haves

• Exposure to optical or high-speed analog interfaces.
• Working knowledge of SKILL, TCL, or Python for layout automation or design-flow optimization.
• Experience collaborating with international teams in the U.S., Canada, and Argentina.
• Strong organizational skills, attention to detail, and follow-through.
• Ability to multitask and prioritize in a fast-paced, dynamic environment.
• Proactive, eager-to-learn mindset and excellent problem-solving skills.

Responsibilities

• Lead and own physical layout design of complex analog/mixed-signal macros, from floor planning through final verification.
• Collaborate with schematic designers on layout solutions that account for performance, matching, symmetry, and reliability.
• Mentor and guide junior layout engineers and contractors across multiple time zones, promoting layout and verification best practices.
• Perform and debug full-hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools.
• Contribute to chip-level planning, including top-level floor planning, block integration, power grid implementation, and signal routing.
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence.
• Support automation initiatives through scripting and tool customization.

Benefits

• Opportunity to play a foundational role at a high-growth semiconductor startup.
• Exposure to a wide variety of cross-functional teams.
• Collaborative international team culture where ideas and initiative are valued.
• Opportunity to grow alongside Celero as it scales and contributes to the future of the industry.
• Opportunity to help shape the future of AI and data center connectivity.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed