Principal Engineer, Layout Design

SiTime Corporation•Santa Clara, CA

About The Position

The Senior Layout Design Engineer will lead top-chip and block-level work and perform custom analog layout design for CMOS and BiCMOS circuits. The role includes reviewing and coordinating work by offshore layout designers, training junior layout engineers and offshore contractors, contributing to standard layout methodologies across sites, and helping establish processes and procedures that ensure high-quality layout design.

Requirements

BA/BS degree in Layout Design or a related field, or equivalent experience.
15+ years of experience in layout design for analog and full-custom digital blocks.
Experience with TSMC 180nm, 65nm, and 22nm process technologies.
Proficiency with layout editing tools in the Cadence Virtuoso design environment.
Solid working knowledge of DRC, LVS, and ERC debugging using Cadence PVS or Mentor Calibre.
Understanding of layout concepts including parasitics, matching, crosstalk, layout-dependent effects, latch-up, IR drop, electromigration (EM), and deep N-well and NTN isolation.
Ability to solve device-matching, electromigration, signal-integrity, and power-distribution challenges while meeting area constraints.
Experience with chip-level floorplanning and analog block integration.
Experience with chip-level integration, verification, and tape-out.
Ability to use productivity-enhancing tools and design scripts to automate and improve workflow efficiency.
Must be able to lift, push, and pull up to 5 lbs.

Nice To Haves

Strong attention to detail; organized, accurate, and able to develop efficient layout techniques.
Proven track record of delivering work on time.
Self-motivated team player with strong communication skills.
Ability to work effectively in a fast-paced, collaborative team environment.

Responsibilities

Collaborate remotely with local and global design and layout teams across multiple design centers and time zones.
Lead and perform custom analog layout design at chip, functional block, block, sub-block, leaf cell, and standard cell levels for CMOS and BiCMOS circuits.
Execute schematic-driven layout design while adhering to design constraints.
Create area-efficient functional block layouts that meet circuit design requirements.
Develop top-chip and block-level floor plans, power distribution networks, shielding structures, and device-matching layouts.
Verify layouts and ensure successful DRC, LVS, and ERC signoff.
Perform chip-level routing and other layout-related activities.
Own chip-chip integration, verification, and tape-out activities.
Provide support for additional projects as required by management.
Train and mentor junior layout engineers and offshore layout contractors.
Contribute to common best practices and workflows across all sites.
Help establish and improve processes and procedures to achieve high layout quality.