Principal Analog IC Design Engineer, High Speed SerDes
Cadence Design Systems•San Jose, CA
•$136,500 - $253,500•Onsite
About The Position
The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.
Requirements
- Minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development.
- Thorough understanding of jitter and signal equalization techniques.
- Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators.
- Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment.
- Proficiency in using CAD tools for circuit simulation, layout, and physical verification.
- MS or PhD in EE
Nice To Haves
- Working knowledge of a set of common SerDes standards and their electrical requirements.
- Cadence tool experience.
- Lab test experience.
- Design experience at >10Gbps.
- Design experience in <28nm technologies.
Responsibilities
- Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.
Benefits
- Incentive compensation: bonus, equity
- Paid vacation
- Paid holidays
- 401(k) plan with employer match
- Employee stock purchase plan
- A variety of medical, dental and vision plan options
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What This Job Offers
Job Type
Full-time
Career Level
Principal
