Power Engineer

Wipro•Sunnyvale, CA

About The Position

Wipro is seeking a Power Engineer to own power-analysis flows used by a large silicon team to estimate and sign off power on SoCs, from RTL through gate level. The role develops and releases in-house tools built around Synopsys power tools, supports design teams running those tools, conducts full-chip power studies, and works with Synopsys to resolve tool issues. The team also uses AI agents to launch runs, debug failures, and generate reports; this role maintains and extends that automation. The engineer will build and maintain Python and Tcl wrappers for Synopsys PrimePower, PrimeTime PX, PrimePower RTL, and RTL Architect. The work spans gate-level and RTL power analysis, flow releases and regressions, power-run support, analysis of results, issue diagnosis, and production of power data for other teams. The position also includes maintaining AI-agent automation for run management, failure analysis, input checking, and bug filing.

Requirements

8+ years in SoC power analysis or low-power methodology, including 3+ years building flows used by other engineers.
Hands-on gate-level power analysis with PrimePower or PrimeTime PX, including averaged and time-based modes, FSDB and SAIF annotation, glitch power, and vectorless analysis.
RTL power estimation experience with PrimePower RTL, RTL Architect, or an equivalent tool such as Cadence Joules.
Knowledge of low-power design, including UPF, power domains and switches, isolation and retention, clock gating, multiple voltages, and memory power states.
Strong Python skills for production tools used by many engineers, including command-line tools, YAML and template-driven configuration, tests, and code review.
Tcl experience in Synopsys shells, plus csh and bash.
Working knowledge of implementation data: Liberty libraries, netlists, SDC, SPEF, and UPF from synthesis and place-and-route.
Ability to trace problems from logs and reports to root cause and explain power results clearly to designers and architects.
Experience with Linux, compute farms such as LSF, version control, and code review.
Mandatory skill: VLSI Physical Place and Route.
The posting also lists experience of 3–5 years.

Responsibilities

Develop, maintain, and release Python and Tcl wrappers around Synopsys PrimePower, PrimeTime PX, PrimePower RTL, and RTL Architect for gate-level and RTL power analysis.
Manage versioned tool releases, release notes, user guides, tutorials, fixes to released versions, and user support in internal Q&A forums.
Keep nightly regression suites passing on reference designs across process nodes and add a test for every fix.
Support design teams’ power runs by setting up netlists, SDC, SPEF, UPF, libraries, and activity files; debugging failed runs; and assessing result reliability.
Conduct power studies on large designs, including campaigns of more than 100 tests on a full-chip network-on-chip.
Derive power metrics including energy per byte, per-block and per-power-domain attribution, clock-gating efficiency, and glitch and leakage breakdowns.
Investigate root causes of tool, library, and flow problems, including memory power rails, power-switch definitions, and PDK updates.
Build small testcases and work with Synopsys support and R&D on tool problems.
Produce power-tracker spreadsheets, dashboards, and power maps for thermal and IR-drop tools.
Build and maintain AI-agent automation for launching and monitoring runs, analysing failures, checking inputs, and filing bugs automatically.