Physical Design/Implementation Engineer-Staff

Qualcomm • Austin, TX

34d • $145,600 - $218,400

About The Position

Qualcomm Technologies, Inc. is seeking a Staff Physical Design/Implementation Engineer for its ASICs Engineering group. The role focuses on end-to-end power, performance, and area (PPA) optimization across synthesis and physical implementation, including floorplanning, placement, clock tree synthesis, routing, and timing and power signoff. The engineer will work with advanced technology nodes and address associated physical-design challenges, while carrying timing intent from synthesis through physical closure.

The position includes timing closure for multi-clock, multi-corner, multi-mode designs and low-power implementation using UPF. It also involves applying power-optimization techniques across synthesis and physical design. The role requires hands-on familiarity with industry-standard implementation, synthesis, timing-analysis, equivalence-checking, and low-power signoff tools, as well as scripting and software-engineering practices.

Requirements

• Hands-on experience in synthesis, place and route, physical design, and timing and power signoff; the role summary states 5 to 10 years of experience.
• Bachelor's degree in Science, Engineering, or a related field and 4+ years of relevant ASIC design, verification, validation, integration, or related work experience; OR a master's degree and 3+ years; OR a PhD and 2+ years.
• Proficiency in Python and Tcl, and familiarity with version control, configuration management, and regression practices.
• Familiarity with PnR tools such as Innovus or ICC2 and synthesis tools such as Fusion Compiler or Genus.
• Hands-on experience with advanced technology nodes and awareness of node-specific PPA levers and physical constraints.
• Knowledge of Static Timing Analysis tools such as PrimeTime or Tempus, LEC, and low-power signoff tools.
• Proficiency in VLSI front-end and back-end design steps, including synthesis, QoR optimization, floorplanning, placement, CTS, routing, and equivalence checking.
• Strong focus on owning power, performance, and area metrics.

Nice To Haves

• Master's degree in Electrical or Electronic Engineering, Computer Engineering, or Computer Science.
• 6+ years of ASIC design, verification, validation, integration, or related work experience.
• 2+ years of experience with architecture and design tools.
• 2+ years of experience with scripting tools and programming languages.
• 2+ years of experience with design verification methods.
• 1+ year of experience in a role requiring interaction with senior leadership, such as Director level and above.
• Knowledge of computer architecture and experience in high-speed, low-power processor design.

Responsibilities

• Drive end-to-end PPA optimization across synthesis and physical implementation rather than treating them as separate handoffs.
• Perform physical synthesis, floorplanning, placement, clock tree synthesis, and routing using industry-standard tools.
• Address advanced-node challenges including double or multi-patterning, pin access, cell legalization, and advanced DRC rules.
• Write and tune timing constraints for synthesis, static timing analysis, timing closure, and pipelining, and carry timing intent through physical closure.
• Drive area recovery, leakage and dynamic power reduction, and performance improvements while balancing synthesis QoR and physical implementation trade-offs.
• Close timing for multi-clock-domain, multi-corner, multi-mode designs at both synthesis and physical-design stages.
• Implement low-power designs using UPF, including power gating, multi-voltage domains, and level-shifter and isolation-cell placement and routing.
• Apply power-optimization techniques such as clock gating, cell sizing, Vt swapping, and buffer or inverter insertion and optimization.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants, except for employees on sales-incentive plans.
• Competitive benefits package.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior