Physical Design Engineer (PnR / PPA / Timing Closure)

Wipro • Mountain View, CA

4d • Onsite

About The Position

Wipro Limited is seeking a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. The role involves driving block-level physical design implementation from netlist to GDSII, performing various stages of the physical design flow, and collaborating with cross-functional teams to ensure successful tapeout and design convergence within project schedules.

Requirements

• Strong experience in Physical Design and PnR flow.
• Hands-on expertise in: Floorplanning, Placement & Optimization, Clock Tree Synthesis (CTS), Routing, Timing Closure, Static Timing Analysis (STA), Timing Constraints (SDC), EMIR Analysis, PPA Optimization.
• Experience with industry-standard EDA tools such as Synopsys Fusion Compiler / ICC2, PrimeTime, Cadence Innovus (optional), RedHawk / Voltus (EMIR).
• Good understanding of low-power design techniques and signoff methodologies.
• VLSI Physical Place and Route experience.
• 8-10 Years of experience.

Nice To Haves

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem-solving skills.
• Experience working with cross-functional silicon teams.

Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Benefits

• Full range of medical and dental benefits options
• Disability insurance
• Paid time off (inclusive of sick leave)
• Other paid and unpaid leave options

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree