ASIC Physical Design Engineer — Synthesis and Timing – (Associate or Experienced)

Boeing•El Segundo, CA

4d•$98,600 - $162,150•Onsite

About The Position

Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC Physical Design Engineers – Synthesis and Timing to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products to support advanced digital subsystem development in an aerospace environment in El Segundo, CA. We are hiring an ASIC Physical Design Engineer — Synthesis and Timing to help implement advanced SoCs used in mission-critical satellite and space applications. You will own portions of the full physical design flow—from synthesis and STA through ECOs and tapeout—collaborating closely with architecture, RTL, verification and outside companies. Boeing continuously shapes the future of aerospace and space systems, advancing U.S. leadership in space while amplifying human creativity and intelligence. As a Boeing engineer, you’ll join a diverse, collaborative team solving high‑impact challenges in complex semiconductor design. If you value a company that supports strong work–life balance and meaningful technical work, Boeing is the place to be.

Requirements

Ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
1+ years of practical experience in synthesis and static timing analysis (STA)
Solid understanding of timing convergence, constraints generation/management, and logic synthesis at block or full‑chip level
Familiarity with DFT, UPF/CPF power intent, ECO implementation, and signoff flows
Experience with industry-standard EDA tools for synthesis, STA, and equivalence checking
Proficiency in scripting (Tcl, Python, Perl) for flow automation and analysis
Strong analytical, problem‑solving, and communication skills

Nice To Haves

Experienced, Level 3: 5+ years of related engineering experience
Bachelor’s Degree or Master's Degree in EE, Computer Engineering/Science, or related field
Active U.S. Secret Security Clearance
Experience with large, timing‑challenging ASIC blocks and cross‑domain timing convergence
Hands‑on experience across the complete physical design flow (synthesis, floorplanning, P&R, CTS, STA, physical verification)
Background in radiation‑hardened or space‑qualified ASIC design
Experience working in multi‑disciplinary teams, vendors and with external Backend partners
Familiarity with industry-standard tools and methodologies

Responsibilities

Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation
Ensure clean netlist handoffs and predictable convergence by partnering with RTL, verification, DFT, and backend partner companies
Support chip‑level integration, top‑level timing closure, signoff readiness, and tapeout activities
Contribute to methodology, automation, tool evaluations, and flow documentation
Troubleshoot complex cross‑domain timing issues and propose robust, repeatable fixes