About The Position

Are you ready to design the future of aerospace and defense technology? We are looking for a talented and highly motivated Physical Design Engineer to join our Advanced Microelectronics team. In this role, you will play a critical part in the development of next-generation ASICs and SoCs that power mission-critical systems. Own the physical implementation of complex, high-performance, and low-power designs from netlist through GDSII tape-out. Working alongside a collaborative team of digital design, verification, and systems engineers, you will leverage industry-leading EDA tools to ensure our silicon meets the rigorous performance, power, and area (PPA) targets required for national security applications.

Requirements

  • Must be a U.S. Citizen with an Active U.S. Secret Clearance (or the ability to obtain and maintain one).
  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
  • Proven industry experience in ASIC/SoC physical design and tape-out cycles.
  • Hands-on expertise with Fusion Compiler (or equivalent place-and-route tools like IC Compiler II/Innovus).
  • Deep knowledge of STA and sign-off timing closure using PrimeTime.
  • Experience with EM/IR analysis using Redhawk.
  • Proficiency in physical verification (DRC/LVS) sign-off tools (e.g., Calibre, IC Validator).
  • Strong scripting skills in Tcl, Python, or Perl to automate EDA flows.
  • Exceptional analytical skills and the ability to debug complex layout, timing, or integration issues autonomously.

Responsibilities

  • Drive block-level and chip-level physical implementation, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler.
  • Perform rigorous Static Timing Analysis (STA), constraint validation, and timing closure using Synopsys PrimeTime across multiple corners and operating modes.
  • Conduct dynamic and static IR-drop analysis, as well as Electromigration (EM) checks, using Ansys Redhawk to ensure robust power delivery and design reliability.
  • Execute and debug Design Rule Checks (DRC) and Layout Versus Schematic (LVS) checks to ensure manufacturing compliance and flawless tape-outs.
  • Collaborate with cross-functional teams to refine physical design methodologies, automate repetitive workflows using Tcl/Python, and optimize the overall PPA.

Benefits

  • 15 days of PTO per calendar year
  • 10 paid Holidays per calendar year
  • Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
  • Dental & Vision: Company covers 50% of premiums for Employee and Dependents
  • Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
  • Employee Assistant Program (EAP)
  • 401k - Traditional & Roth
  • Life/AD&D and Long-Term Disability
  • Tuition reimbursement
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