Physical AI SoC Architect

Advanced Micro Devices, Inc • San Jose, CA

9h

About The Position

AMD is seeking an experienced SoC Architect to define next-generation systems-on-chip for automotive, robotics, vision, and Physical AI applications. The role translates real-world workloads and customer use cases into quantitative SoC requirements across compute, memory, bandwidth, interconnect, data movement, power, and end-to-end latency. The architect evaluates alternatives and helps turn system-level requirements into executable SoC designs throughout the development lifecycle.

The position calls for strong system and SoC architecture knowledge, analytical and performance-modeling skills, and an understanding of heterogeneous SoCs, processors, AI acceleration, memory systems, and interconnects. The architect works collaboratively with hardware, software, performance, and customer-facing teams to solve complex system-level problems.

The role is located in San Jose, California; San Diego, California; or Austin, Texas. AMD identifies the posting as an existing vacancy.

Requirements

• Bachelor’s, master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong experience with heterogeneous SoC architecture and system performance analysis.
• Knowledge of x86 and/or ARM or RISC-V processor architecture, cache and memory hierarchies, coherent interconnects, and heterogeneous acceleration.
• Strong understanding of DDR/LPDDR, cache and memory behavior, NoC/interconnect traffic, latency, QoS, and data movement.
• Ability to translate application workloads into quantitative architecture requirements and identify system performance bottlenecks.

Nice To Haves

• Experience with AI/ML inference, computer vision, robotics, automotive, multimedia/imaging, or other complex SoC workloads.
• Experience developing analytical or simulation-based performance models using Python, C/C++, SystemC, MATLAB, or similar tools.
• Experience contributing to architecture, design, verification, or implementation across the SoC development lifecycle.
• Familiarity with embedded system constraints, including power, thermal limits, real-time performance, functional safety, and security.

Responsibilities

• Translate Physical AI, automotive, robotics, and vision workloads into SoC compute, memory, bandwidth, interconnect, and latency requirements.
• Model end-to-end data flows across sensors, CPUs, AI accelerators, memory hierarchy, on-chip interconnect, and I/O.
• Analyze and optimize data placement and movement across DDR memory, caches, on-chip memory, accelerator-local memory, and buffers.
• Correlate AI compute requirements and accelerator performance with memory bandwidth, data movement, utilization, and system-level performance.
• Perform what-if and scaling analyses involving camera count, resolution, frame rate, AI model characteristics, precision, memory configuration, and accelerator performance.
• Develop data-flow diagrams, bandwidth models, traffic timelines, latency budgets, and bottleneck analyses to inform architecture decisions.
• Evaluate architectural alternatives and make performance, power, area, and cost trade-offs.
• Collaborate with SoC, AI, CPU, memory, interconnect, software, and performance teams to optimize end-to-end system performance.
• Support architectural decisions through implementation and execution across the SoC development lifecycle.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior