Senior SoC Architect, RAS

NVIDIA•Santa Clara, CA

2d•$184,000 - $356,500

About The Position

NVIDIA is seeking a Senior Hardware Architect focused on Reliability, Availability, and Serviceability (RAS) for Tegra System-on-Chips. The role defines and drives RAS hardware architecture across advanced CPUs and SoCs, from early concepts through implementation, verification, validation, and production readiness. The work supports resilient computing platforms for datacenters, autonomous vehicles, edge systems, and other high-reliability applications. The architect collaborates with systems architects, RAS specialists, design, verification, validation, firmware, software, and platform teams to develop end-to-end hardware features that improve resiliency, observability, debuggability, error containment, recovery, and serviceability. Space- and radiation-aware design are areas of interest, while the primary focus is broad SoC RAS architecture and delivering features through the product development flow. The role includes creating architectural specifications, requirements, error-handling flows, design guidance, test plans, and architectural models where applicable. It also involves planning verification and validation strategies, supporting silicon debug and failure analysis, and applying RAS principles to high-reliability environments. The position may contribute to patents for novel hardware architecture techniques. Base salary ranges are $184,000–$287,500 for Level 4 and $224,000–$356,500 for Level 5; the role is also eligible for equity and benefits.

Requirements

MS or PhD in computer engineering, electrical engineering, or equivalent experience.
At least 8 years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience.
Strong understanding of SoC RAS, including fault detection, correction, containment, telemetry, recovery, degradation modes, debug visibility, and serviceability mechanisms.
Experience defining and driving hardware architecture features through architecture definition, design implementation, verification planning, validation, debug, and production readiness.
Strong understanding of overall SoC architecture and ability to reason across micro-architecture, full-chip integration, firmware interfaces, software-visible behavior, platform flows, and customer use cases.
Meaningful industry expertise in one or more SoC architecture areas, such as RAS, safety, debug, clocks, resets, interconnects, memory controllers, IO technologies, platform integration, firmware-visible error handling, or diagnostic infrastructure.
Hands-on experience with design verification, silicon validation, fault injection, coverage analysis, resiliency modeling, diagnostic development, or reliability validation methodology.
Excellent analytical, written, verbal, and interpersonal skills, with the ability to work across architecture, design, verification, firmware, software, validation, and customer-facing teams.

Nice To Haves

Familiarity with radiation effects, space operation, or other high-reliability deployment environments, including how hardware architecture can mitigate single-event effects and related reliability risks.
Demonstrated history of architecting and delivering complex SoC RAS features across design, verification, validation, and production phases.
Deep familiarity with architectural resiliency techniques such as ECC, parity, redundancy, replay, checkpoint/restart, scrubbing, isolation, containment, telemetry, error logging, recovery flows, and graceful degradation.
Experience debugging hardware failures in simulation, emulation, post-silicon validation, production, customer deployments, or other high-reliability systems.
Familiarity with Design for Debug, Design for Test, Design for Reliability, silicon observability, fault-injection methodology, and coverage-driven validation flows.

Responsibilities

Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform components.
Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
Work with design, verification, validation, firmware, software, and platform teams to make RAS features implementable, verifiable, debuggable, and aligned with system requirements.
Assess how RAS mechanisms interact with performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
Create hardware specifications, architectural requirements, error-handling flows, design guidance, test plans, and architectural models in SystemC, C/C++, Python, or other relevant modeling environments where applicable.
Plan and review verification and validation strategies, including error injection, recovery validation, coverage analysis, resiliency modeling, and architecture reviews.
Assist with failure analysis and silicon debug for lab, post-silicon, production, and field findings; develop diagnostic screens and localization methods for latent, intermittent, and environment-sensitive failures.
Apply RAS architecture principles to high-reliability deployment environments, including space-aware and radiation-aware use cases.
Follow industry standards and research related to RAS, functional safety, semiconductor reliability, debuggability, verification, validation, and silicon testing.
Patent novel hardware architecture techniques that improve system resiliency, observability, serviceability, and recovery.