Senior SoC Architect, RAS

NVIDIA•Austin, TX

1d•$224,000 - $356,500

About The Position

NVIDIA is seeking a Senior Hardware Architect focused on Reliability, Availability, and Serviceability (RAS) for Tegra System-on-Chips. The role defines, drives, and delivers RAS hardware architecture across advanced CPUs and SoCs, from early architectural concepts through design implementation, verification, validation, and production readiness. The work supports datacenters, autonomous vehicles, edge systems, and other high-reliability applications, with space-aware and radiation-aware design as areas of interest. The architect collaborates with systems architects, RAS experts, design, verification, validation, firmware, software, and platform teams to develop end-to-end hardware RAS features that improve system resiliency, observability, debuggability, error containment, recovery, and serviceability. The position requires reasoning across overall SoC architecture and its interactions with performance, power, resets, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software. It also involves architectural specifications and models, verification and validation planning, silicon failure analysis and debug, and following relevant industry standards and research. The role may contribute novel hardware architecture techniques through patents.

Requirements

MS or PhD degree in computer engineering, electrical engineering, or equivalent experience.
At least 8 years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience.
Strong understanding of SoC RAS, including fault detection, correction, containment, telemetry, recovery, degradation modes, debug visibility, and serviceability mechanisms.
Experience defining and driving hardware architecture features through the full development lifecycle, including architecture definition, design implementation, verification planning, validation, debug, and production readiness.
Strong understanding of overall SoC architecture and the ability to reason across micro-architecture, full-chip integration, firmware interfaces, software-visible behavior, platform flows, and customer use cases.
Meaningful industry expertise in one or more SoC architecture areas, such as RAS, safety, debug, clocks, resets, interconnects, memory controllers, IO technologies, platform integration, firmware-visible error handling, or diagnostic infrastructure.
Hands-on experience with design verification, silicon validation, fault injection, coverage analysis, resiliency modeling, diagnostic development, or reliability validation methodology.
Excellent analytical, written, and verbal interpersonal skills, with the ability to work effectively across architecture, design, verification, firmware, software, validation, and customer-facing teams.

Nice To Haves

Familiarity with radiation effects, space operation, or other high-reliability deployment environments, including how hardware architecture can mitigate single-event effects and related reliability risks.
Demonstrated history of architecting and delivering complex SoC RAS features across design, verification, validation, and production phases.
Deep familiarity with architectural resiliency techniques such as ECC, parity, redundancy, replay, checkpoint/restart, scrubbing, isolation, containment, telemetry, error logging, recovery flows, and graceful degradation.
Experience debugging hardware failures in simulation, emulation, post-silicon validation, production, customer deployments, or other high-reliability systems.
Familiarity with Design for Debug, Design for Test, Design for Reliability, silicon observability, fault-injection methodology, and coverage-driven validation flows.

Responsibilities

Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components.
Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
Work with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements.
Analyze how RAS mechanisms interact with SoC performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
Create hardware specifications, architectural requirements, error-handling flows, design guidance, test plans, and, where applicable, architectural models in SystemC, C/C++, Python, or other modeling environments.
Plan and review verification and validation strategies for RAS mechanisms, including error injection, recovery validation, coverage analysis, resiliency modeling, and architecture reviews.
Assist with failure analysis and silicon debug for lab, post-silicon, production, and field findings; develop diagnostic screens and localization methods for latent, intermittent, and environment-sensitive failures.
Apply RAS architecture principles to high-reliability environments, including space-aware and radiation-aware use cases involving single-event effects, memory or logic corruption, and cumulative radiation exposure.
Follow industry standards and research related to RAS, functional safety, semiconductor reliability, debuggability, verification, validation, and silicon testing.
Patent novel hardware architecture techniques that improve system resiliency, observability, serviceability, and recovery.