Lead SoC Architect

Advanced Micro Devices, Inc•San Jose, CA

About The Position

AMD is seeking a senior technical leader to define the architecture and technical direction of next-generation SoCs for applications including AI, Data Center, Security, Communications, and Embedded Computing. The role covers heterogeneous compute, advanced memory systems, leading-edge I/O, high-performance interconnects, and AI, networking, storage, compute, and crypto acceleration. The architect will influence long-term silicon strategy and guide teams across architecture, design, verification, physical implementation, software, and customer engineering, contributing to AMD’s Adaptive, Embedded, and Custom SoCs. The successful candidate is an industry expert in heterogeneous SoC architecture with deep knowledge of processor and acceleration subsystems, advanced protocols, and high-bandwidth memory and interconnect design. They will lead complex technical programs, make performance, power, area, cost, and manufacturability tradeoffs, and collaborate with internal and external partners and customers. The position is located in San Jose, California, or Austin, Texas. AMD states that benefits are described in its “AMD benefits at a glance” materials; specific benefits are not listed in this posting.

Requirements

Recognized expertise in heterogeneous SoC architecture.
Deep experience with CPUs, AI/networking/storage/compute/crypto acceleration, advanced protocols, and high-bandwidth memory/interconnect design.
Demonstrated leadership experience on complex technical programs.
Ability to balance performance, power, area, and cost tradeoffs.
Strong communication and ability to work in fast-paced, cross-domain environments.
Track record of delivering differentiated SoC solutions.
MS or PhD in Electrical Engineering, Computer Engineering, or a related field.

Nice To Haves

Proven track record defining and delivering complex heterogeneous SoC architectures in advanced process nodes.
Expertise in x86-, ARM-, or RISC-V-based processor subsystems and heterogeneous acceleration.
Deep technical knowledge of PCIe, CXL, Ethernet, DDR, UCIe, and UAL specifications and how protocol features are used in SoCs or systems.
Strong technical leadership across interconnect fabrics, memory, I/O technology, and subsystems.
Familiarity with high-speed I/O protocols, multi-chiplet partitioning, and chiplet interconnect standards.
Proficiency with architectural modeling and performance simulation frameworks.
Ability to influence silicon strategy, ecosystem partners, and customer roadmaps.
Patents, publications, or major architectural wins.

Responsibilities

Own and lead the architecture of next-generation SoCs, including multiprocessor subsystems, coherent and non-coherent interconnects, memory and cache hierarchies, advanced I/O, and AI, networking, storage, compute, and crypto acceleration.
Define long-term SoC architectural strategy aligned with product roadmaps and customer requirements.
Develop detailed SoC architecture specifications covering compute, memory, accelerators, interconnect, RAS, security, boot/configuration, and SoC management.
Guide cross-functional execution across RTL design, verification, physical design, firmware, software, and platform teams.
Collaborate with customers in AI, Data Center, Security, Communications, and Embedded Computing, translating RFQs and use cases into SoC architectural requirements.
Evaluate processor IP and emerging technologies, including x86, ARM, and RISC-V cores, compute accelerators, and PCIe, CXL, Ethernet, DDR, UCIe, and/or UAL protocols.
Lead PPA tradeoff decisions, aligning architecture with cost, performance, power, and manufacturability targets.
Innovate in hardware security, heterogeneous coherency, traffic shaping, system QoS, and power management.
Mentor architects and strengthen architectural rigor, methodology, and technical leadership across the organization.
Create flexible, modular subsystem architectures suitable for chiplet, monolithic, or 3D form factors.
Author clear and concise architecture specifications and guide pre-silicon design and verification as well as post-silicon validation.