Digital Design Engineer
Credo•San Jose, CA
•$130,000 - $200,000•Onsite
About The Position
Team Credo is looking for a PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products. The ideal candidate possesses strong digital design fundamentals, hands-on RTL development experience, and a good understanding of high-speed SerDes architecture. This position will be onsite at our San Jose, CA HQ.
Requirements
- BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of digital design experience (or equivalent expertise for senior candidates).
- Strong RTL development skills using System Verilog.
- Experience designing high-speed communication or DSP hardware.
- Solid understanding of fixed-point arithmetic RTL implementation.
- Experience with ASIC development flow (e.g. Lint, CDC/RDC, Synthesis, Timing analysis).
- Familiarity with EDA tools from Synopsys, Cadence, or Siemens.
- Strong debugging and problem-solving skills.
Nice To Haves
- Experience with high-speed SerDes standards such as PCIe, Ethernet.
- Understanding of SerDes receiver and transmitter architectures, and DSP algorithms (e.g. LMS adaptation, timing recovery).
- Familiarity with Python or other scripting languages.
- Understanding of MATLAB or C/C++ modeling.
- Knowledge of mixed-signal PHY architecture and analog/digital interfaces.
- Experience of mixed-signal PHY simulations.
- Experience supporting silicon bring-up and post-silicon validation.
- Exposure to advanced process nodes (7nm, 5nm, 3nm, or beyond).
Responsibilities
- Define RTL micro-architecture for digital PHY and SerDes DSP functions.
- Develop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops).
- Work with system architects and algorithm teams to translate DSP algorithms into RTL.
- Optimize designs for performance, power, area, and latency.
- Verify DSP modules and debug functional issues.
- Support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
- Analyze silicon bring-up data with validation teams to resolve issues.
- Support PHY integration and system-level debugging.
Benefits
- discretionary bonus
- equity
- medical and other benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
