PHY Design Verification Engineer

Apple • San Diego, CA

1d

About The Position

Join Apple’s wireless silicon development team, which develops energy-efficient wireless silicon and technologies that enhance product experiences. The Wireless SoC organization brings together engineering teams across RF/Analog, Systems/PHY/MAC, VLSI/RTL, Design Verification, Emulation, Test and Validation, and FW/SW.

As a PHY Design Verification Engineer, you will perform pre-silicon RTL verification of wireless PHY and its interfaces with the wireless communication SoC. You will collaborate with DV methodologists, designers, and communication systems engineers to build reusable testbenches and verification environments using metric-driven verification methods. You will review PHY subsystem microarchitecture and specifications, develop and refine verification plans, and work with system and design teams to meet coverage targets. The role also supports PHY subsystem validation using Palladium and/or FPGA, and contributes to improvements in DV methodology and flow.

Requirements

• Bachelor’s degree minimum.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Excellent knowledge and experience with ASIC verification flows, including testbench development, constrained-random testing, and code and functional coverage.
• MSEE with 2+ years of verification experience of a wireless or wired communication block/subsystem.
• Verification experience of a wireless or wired communication block/subsystem.
• Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
• Proficiency in shell and Python scripting; Perl scripting is also listed.
• Team player with excellent communication skills; self-motivated and well organized.

Nice To Haves

• Experience using a Matlab/C reference model and bit-accurate verification.
• Experience using AI technologies in data mining/analysis.
• Experience with Palladium/FPGA validation.

Responsibilities

• Review and understand PHY subsystem microarchitecture with system and design teams.
• Create verification plans from specifications, and review and refine them to achieve coverage targets.
• Build block- and subsystem-level testbenches with reference models using DV methodology.
• Architect reusable testbenches and verification environments.
• Develop and execute directed and constrained-random tests; debug failures, manage bug tracking, and work with designers to close issues.
• Create and analyze block- and subsystem-level coverage models, and add test cases to increase coverage.
• Use machine learning and AI technologies to identify design and testbench issues and ensure DV quality.
• Support PHY subsystem validation using Palladium and/or FPGA.
• Work with team members to improve DV methodology and flow.

What This Job Offers

• Job Type: Full-time