PHY Design Verification Engineer

Apple•San Diego, CA

21h

About The Position

Apple’s wireless silicon development team develops wireless SoCs, emphasizing energy efficiency and technologies that transform product experiences. The team spans RF/Analog, Systems/PHY/MAC, VLSI/RTL, Design Verification, Emulation, Test and Validation, and FW/SW engineering. The PHY Design Verification Engineer performs pre-silicon RTL verification of wireless PHY and its interfaces with the wireless communication SoC. The role works with DV methodologists, designers, and communication systems engineers to create reusable test benches and verification environments using metric-driven verification methods. It includes reviewing PHY subsystem microarchitecture, developing and refining verification plans from specifications, building block- and subsystem-level test benches with reference models, running directed and constrained-random tests, analyzing coverage, debugging and tracking issues, and supporting validation using Palladium and/or FPGA. The engineer also applies machine learning and AI technologies to identify design and test-bench issues and works with colleagues to improve verification methodology and flows.

Requirements

Bachelor’s degree and a minimum of 10 years of relevant industry experience.
Verification experience with wireless or wired communication blocks or subsystems.
Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
Excellent knowledge and experience of ASIC verification flows, including test-bench development, constrained-random testing, and code and functional coverage.
Experience using MATLAB or C reference models and bit-accurate verification.
Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee.
Proficiency in shell and Python scripting; Perl scripting is also required.
Experience using AI technologies in data mining or analysis.
Experience with Palladium or FPGA validation.
Team player with excellent communication skills; self-motivated and well organized.

Responsibilities

Review and understand PHY subsystem microarchitecture with system and design teams.
Create verification plans from specifications and review and refine them to achieve coverage targets.
Build block- and subsystem-level test benches with reference models using established design verification methodology.
Architect reusable test benches.
Develop and execute directed and constrained-random tests.
Debug failures, manage bug tracking, and work with designers to close identified issues.
Create and analyze block- and subsystem-level coverage models and add test cases to increase coverage.
Use machine learning and AI technologies to identify design and test-bench issues and ensure design verification quality.
Support PHY subsystem validation using Palladium and/or FPGA.
Work with team members to improve design verification methodology and flows.