Photonics Layout Engineer (Onsite/Hybrid)

Voyant Photonics•New York, NY

2d•$120,000 - $190,000•Onsite

About The Position

Voyant Photonics is hiring a Photonics Layout Engineer to develop and implement silicon photonic integrated circuit (PIC) layouts for optical circuit switching in AI data centers and chip-scale FMCW LiDAR sensing. The role owns PIC layouts from initial floorplanning through tapeout, including component-level test structures and large-scale system PICs. The engineer will translate photonic schematics and design requirements into efficient, manufacturable GDSII layouts and help address dense waveguide routing, multilayer optical interconnects, and die- and reticle-level floorplanning. The position also involves developing reusable layout libraries and automation methods, integrating photonic and electrical layouts, and supporting physical verification and foundry tapeout submissions. The engineer will work closely with photonic designers, packaging engineers, and foundry partners in a fast-paced startup environment. Voyant’s lab and office are in Midtown Manhattan, with optical tables, lab benches, and electronics alongside traditional office space. Work is hands-on and primarily in person, but schedules are not rigidly 9-to-5; customer calls across time zones may start early or run late, with schedules adjusted around them. The company describes its environment as high-trust and high-accountability, where employees own meaningful work, move quickly, and may take on varied responsibilities. Voyant provides catered lunch every day at headquarters.

Requirements

B.S. or M.S. in Electrical Engineering, Photonics, Physics, Optical Engineering, or a related field.
At least 2 years of experience in photonic integrated circuit layout, preferably in silicon photonics or a similar platform.
Proficiency with photonic layout tools such as GDSFactory, IPKISS, KLayout, or equivalent.
Strong Python scripting skills, including experience with layout automation or parameterized designs.
Experience with photonic waveguide routing, component placement, and chip-level layout integration.
Familiarity with silicon photonics foundry PDKs, design rules, and tapeout processes.
Strong attention to detail and problem-solving skills, and ability to collaborate in a multidisciplinary team.

Nice To Haves

Experience with large-scale PIC layout, optical switching networks, or complex photonic routing architectures.
Experience with multilayer silicon/silicon nitride photonic platforms and interlayer optical transitions.
Experience developing automated routing, placement optimization, or layout generation algorithms.
Familiarity with Cadence Virtuoso, SKILL, or electrical layout and EDA integration.
Experience with photonic-electronic co-layout, packaging interfaces, or commercial silicon photonics foundry tapeouts.

Responsibilities

Develop and implement layouts for photonic integrated circuits, from component-level test structures to large-scale system PICs.
Translate photonic schematics and design requirements into efficient, manufacturable GDSII layouts.
Implement dense waveguide routing, multilayer optical interconnects, and die- and reticle-level floorplanning.
Develop and maintain parameterized photonic component cells (PCells) and reusable layout libraries.
Create Python-based scripts and automation tools for layout generation, routing, and design verification.
Integrate photonic and electrical layouts, including electrical routing, contact pads, and packaging interfaces.
Perform and debug physical verification, including DRC, LVS, and optical connectivity checks.
Collaborate with photonic designers, packaging engineers, and foundry partners to optimize layouts and support tapeout submissions.