Photonics AI Engineer - Layout & Verification - Santa Clara, CA

Xanadu•,

3d•$160,000 - $210,000

About The Position

Xanadu is hiring a Photonics AI Engineer to own layout and physical verification for a fast-paced path-finding team. The role turns validated components and circuit schematics into functional, verified, tapeout-ready devices, including full reticles, test structures, and process-monitor vehicles for MPW shuttles and dedicated full mask sets. The work depends on an automated, repeatable cadence, so the engineer will build layout generation, verification, and agentic AI tooling. The engineer will own GDS/OASIS mask layout from released building blocks through foundry submission, including hierarchical device layouts, routing and floorplanning, physical verification, mask data preparation, reticle planning, sign-off, and tapeout review. They will also design test structures and on-chip monitors and collaborate with component designers, fabrication engineers, and test engineers to ensure layouts align with process capabilities. The role primarily uses Python, scripted layout frameworks such as gdsfactory and IPKISS, GitHub, Docker, cloud compute, and agentic AI tools. Xanadu offers a base salary range of $160,000–$210,000 USD, with eligibility for equity and benefits.

Requirements

Fluency with modern AI tooling in day-to-day work, such as coding agents, LLM-driven automation, or agentic pipelines, and a track record of building personal tools.
Participation in multiple tapeouts with direct ownership of layout, verification, and sign-off.
Enthusiasm for quickly adopting new AI capabilities and reshaping workflows around them.
BSc in Engineering, Physics, or a related field.
Strong experience with scripted photonic mask design and layout using gdsfactory, IPKISS, KLayout, or similar.
Experience generating production GDSII/OASIS layouts for dedicated full mask sets.
Solid physical verification experience, including DRC and LVS with foundry-provided and custom rule decks.
Experience working from a PDK or a library of reusable layout building blocks.
Strong Python skills, including testing, code review, and version control.
Attention to detail and judgment about which checks matter under schedule pressure.
Comfort operating in a fast-paced environment with hard external deadlines.
Proficiency with Python, scripted layout frameworks such as gdsfactory and IPKISS, GitHub, Docker, cloud compute, and agentic AI tools.

Nice To Haves

Interest in applying ML/AI to design automation problems; prior hands-on experience in any domain is a plus.
MSc or PhD in Engineering, Physics, or a related field.
Experience building agentic systems or AI tooling for a technical domain.
Experience applying LLMs or ML/AI to EDA-adjacent problems such as layout generation, verification triage, or design-data extraction.
Experience with automated routing or placement for large-scale photonic integrated circuits.
Experience with mask data preparation, custom filler patterns, and multi-layer reticle floorplanning.
Experience with schematic-driven layout and photonic circuit simulation.
Experience coordinating tapeouts with foundry partners.
Familiarity with quantum photonics or quantum computing hardware.

Responsibilities

Own end-to-end GDS/OASIS mask layout for test structures, path-finding vehicles, and production tapeouts.
Translate circuit schematics and component libraries into hierarchical, verified device layouts using scripted layout frameworks.
Own the flow from PDK and released building blocks through signed-off mask sets, keeping it fast and repeatable.
Build automated routing, floorplanning, and assembly tools for large-scale photonic circuits, targeting minimum routing loss and footprint.
Own physical verification, including DRC, LVS, connectivity and netlist integrity, custom rule decks, and mask data preparation.
Build agentic AI tooling for layout and verification, including layout-code generation and refactoring, DRC triage, test-structure and DOE-array generation, schematic-to-layout reconciliation, and tapeout review packages.
Own the tapeout process, including reticle floorplanning, checklists, sign-off criteria, and submission to foundry partners.
Design test structures and on-chip monitors to help ensure returned wafers answer the design team's questions.
Work with component designers, fabrication engineers, and test engineers to align layout practices with process capability.