Photonic IC Design Engineer, Chip-to-System Integration

K2 Space•Seattle, WA

About The Position

K2 is seeking a Photonic IC Design Engineer focused on chip-to-system integration to design photonic integrated circuits (PICs) and the packages that connect them to external systems. The work includes developing compact, lightweight, low-cost, rugged photonic hardware for spacecraft constellation-scale use. The engineer will own optical and electrical interfaces between the chip and system, including optical coupling and fiber attachment, high-speed modulators and RF interfaces, and bias and tuning control. The role also ensures assemblies can withstand launch and years in orbit, with coupling-loss, modulator, and bandwidth performance feeding into system link budgets. The engineer will collaborate with systems, photonics test and automation, RF, ASIC, and manufacturing teams, as well as external foundry and packaging partners. As a founding member of the photonics team, this person will help establish how K2 designs, packages, and qualifies photonic hardware. The position requires a PhD or MS in electrical engineering, optics, physics, or a related field, or a bachelor's degree with equivalent experience. Compensation is a base salary of $130,000–$200,000 plus company equity. Salary depends on factors including knowledge and skills, education, and experience. The company offers a comprehensive benefits package. The person hired must be a U.S. person as defined by the cited ITAR regulation or otherwise eligible for a federally issued export control license.

Requirements

PhD or MS in electrical engineering, optics, physics, or a related field, or a bachelor's degree with equivalent experience.
PIC designs taken through tapeout on one or more commercial integrated photonics platforms, such as silicon photonics, silicon nitride, indium phosphide, or thin-film lithium niobate, with fabricated devices characterized in a laboratory.
Hands-on experience at the chip boundary, including optical I/O design with fiber attachment or packaging, or high-speed modulator and RF design measured with a VNA, including S-parameters and electro-optic bandwidth.
Experience with photonic device simulation tools such as Meep, Tidy3D, Lumerical FDTD, FEM, or EME; layout tools such as KLayout, gdsfactory, or Cadence; and Python for automation and data analysis.

Nice To Haves

Experience using 3D mechanical CAD such as SolidWorks, Inventor, or Fusion for package parts or fixtures, including producing machine-shop-ready drawings.
Radiation, thermal-vacuum, or vibration testing of photonic or electronic devices.
Experience with inverse design or topology optimization of couplers and other optical I/O devices.
RF package or board design to tens of GHz, using tools such as HFSS or Sonnet.
Experience with heterogeneous or 3D integration and co-packaged optics.
Experience building hardware for space or other harsh environments.
Experience with modulator bias control, resonator locking, or other closed-loop control of photonic devices.
Background in RF or microwave engineering.

Responsibilities

Design, simulate, and lay out PIC devices and circuits—including edge and grating couplers, spot-size converters, photodetectors, and passive components—from specification through tapeout on commercial integrated photonics foundry platforms.
Design high-speed modulators, including traveling-wave Mach-Zehnder and ring modulators, their electrodes, terminations, and RF launches; co-design them with RF and ASIC engineers to meet driver and TIA specifications.
Implement hardware for bias and tuning control, including heaters and monitor photodiodes; define drive and readout interfaces with electronics engineers and bring up closed-loop modulator bias and resonator locking, verified over temperature and radiation.
Set optical I/O requirements, including coupling loss, alignment tolerance, polarization, and die I/O placement, and coordinate these with chip floorplans and system link budgets.
Design package mechanics in 3D CAD, including PIC carriers and submounts, fiber-array V-groove and lid geometry, strain relief, and alignment and assembly fixtures; tie tolerance stack-ups to the coupling-loss budget.
Drive radiation, thermal-vacuum, and vibration qualification of photonic devices and packages by writing test plans, leading campaigns with internal test and reliability engineers and external facilities, and translating results into design rules.
Partner with the photonics test and automation team on characterization by defining test plans and pass/fail metrics, designing test structures and probe- and fiber-array-compatible layouts, supporting automated measurement bring-up and validation, and using shared data to connect simulation, measurement, and design.
Carry the high-speed electrical path through the package, including wirebond or flip-chip transitions and RF interconnects to drive electronics.
Present designs at preliminary and critical design reviews.