PhD Engineering Internship 2027

Riverlane • Boston, MA

11d • Hybrid

About The Position

Riverlane is hiring a PhD Engineering Intern to investigate the classical computing architectures needed to support scalable, fault-tolerant quantum computers. The project sits at the intersection of quantum error correction (QEC), computer architecture, and hardware-software co-design. Depending on the project, the intern may explore efficient decoding or predecoding, model the classical resources required by fault-tolerant quantum programs, or examine how decoding workloads can be distributed across computing-system levels.

The intern will work with Riverlane researchers and engineers in Cambridge, Massachusetts, with support from a dedicated supervisor. The work will contribute to understanding how QEC systems can meet the performance requirements of increasingly large quantum computers. The internship is full-time for 10 to 12 weeks and is fixed-term. Applicants must be authorized to work in the United States for the duration of the internship. The role is hybrid and based at Riverlane’s US office in Cambridge, Massachusetts.

Riverlane develops quantum error-correction technology and partners with quantum hardware providers and government agencies. The company describes its working environment as diverse and collaborative, bringing together expertise across software and hardware development, quantum information theory, physics, mathematics, and other technical fields. It offers free snacks and refreshments and regular social and cultural events. Reasonable expenses incurred as part of the role, such as approved travel to meetings or conferences, will be reimbursed; travel to Cambridge at the beginning or end of the internship and accommodation during the internship are not covered. The intern will be required to sign an agreement assigning ownership of intellectual property produced during the internship to Riverlane.

Requirements

• Currently pursuing a PhD in Computer Science, Computer Engineering, Electrical Engineering, Physics, Mathematics, or another related technical field.
• Research experience in at least one of the following areas: quantum error correction or fault-tolerant quantum computing; computer architecture or quantum-classical systems; decoding algorithms or error-correcting codes; FPGA, ASIC, or digital hardware design.
• Experience developing computational models, simulations, or research software.
• Proficiency in Python, C, C++, or another relevant programming language.
• Strong understanding of computer systems and architecture.
• Excellent analytical and problem-solving skills.
• Ability to communicate complex technical ideas clearly.
• Ability to take initiative and work effectively with researchers and engineers from different disciplines.
• Authorization to work in the United States for the duration of the internship.
• Availability to work full-time for 10 to 12 weeks.
• If using CPT, OPT, or another form of student employment authorization, responsibility for obtaining the necessary approval before the start date.

Nice To Haves

• Experience researching quantum LDPC or surface codes.
• Familiarity with QEC decoding or predecoding techniques.
• Experience exploring the classical resource requirements of fault-tolerant quantum computing.
• Experience with hardware-software or compiler-hardware co-design.
• Experience with RTL, SystemVerilog, FPGA, or ASIC development workflows.
• Understanding of latency, bandwidth, or power constraints affecting quantum control and decoding systems.
• Experience with scientific computing, quantum circuit simulation, or QEC simulation tools.
• Contributions to academic publications, open-source software, or collaborative research projects.

Responsibilities

• Contribute to a research project focused on the classical systems and architectures required for scalable quantum error correction.
• Investigate methods for reducing compute, communication, memory, latency, or power requirements associated with QEC.
• Develop algorithms, simulations, or architectural models to evaluate potential approaches.
• Explore trade-offs between decoding performance, logical error suppression, and classical resource requirements.
• Consider how QEC workloads could be implemented across software, FPGA, ASIC, or other computing architectures.
• Collaborate with researchers and engineers working across QEC theory, decoding, software, and hardware.
• Analyze results and communicate findings through technical discussions, presentations, and written reports.
• Produce clear, reproducible research code and supporting documentation.

Benefits

• Reimbursement of reasonable expenses incurred as part of the role, such as approved travel to meetings or conferences.
• Free snacks and refreshments.
• Regular social and cultural events.

What This Job Offers

• Job Type: Full-time
• Career Level: Intern
• Education Level: Ph.D. or professional degree