PhD Research Internship 2027

Riverlane•Boston, MA

11d•Hybrid

About The Position

Riverlane is seeking a PhD Research Intern to investigate simulating, running, and decoding quantum error-correction (QEC) experiments. Working with a dedicated supervisor, the intern will frame a research project at the intersection of quantum error correction, computer simulations, computer architecture, and hardware-software co-design. Potential project topics include quantum hardware noise models, efficient QEC experiment simulations, decoding or predecoding methods, classical resource modeling for fault-tolerant quantum programs, and distributing decoding workloads across levels of a computing system. The intern will work alongside Riverlane’s quantum scientists and engineers in Cambridge, Massachusetts. The work will contribute to understanding how QEC systems can meet the performance requirements of increasingly large quantum computers. The internship is full-time for 10 to 12 weeks and is based at Riverlane’s US office in Cambridge, Massachusetts. It is a fixed-term internship for 2027, with a hybrid workplace designation in the posting. Pay is $55.70 per hour, depending on experience. Reasonable role-related expenses, such as approved travel to meetings or conferences, will be reimbursed; travel to Cambridge at the beginning or end of the internship and accommodation are not covered.

Requirements

Currently pursuing a PhD in Physics, Mathematics, Computer Science, Computer Engineering, Electrical Engineering, or another related technical field.
Research experience in at least one of the following areas: running quantum circuits on quantum hardware; decoding algorithms or quantum error-correcting codes.
Experience developing computational models, simulations, or research software.
Proficiency in Python, C, C++, or another relevant programming language.
A strong understanding of computer systems and architecture.
Excellent analytical and problem-solving skills.
Ability to communicate complex technical ideas clearly.
Ability to take initiative and work effectively with researchers and engineers from different disciplines.
Authorization to work in the United States for the duration of the internship; required student employment authorization must be approved before the start date where applicable.
Availability to work full-time for 10 to 12 weeks.
Agreement to assign ownership of intellectual property produced during the internship to Riverlane.

Nice To Haves

Experience researching qLDPC or surface codes.
Familiarity with QEC decoding or predecoding techniques.
Experience exploring the classical resource requirements of fault-tolerant quantum computing.
Experience with scientific computing, quantum circuit simulation, or QEC simulation tools.
Contributions to academic publications, open-source software, or collaborative research projects.
Experience with hardware-software or compiler-hardware co-design.
Understanding of latency, bandwidth, or power constraints affecting quantum control and decoding systems.

Responsibilities

Develop algorithms, simulations, or architectural models to evaluate potential approaches.
Investigate methods for reducing the compute, communication, memory, latency, or power requirements associated with QEC.
Explore trade-offs between decoding performance, logical error suppression, and classical resource requirements.
Collaborate with quantum scientists and engineers working across QEC theory, decoding, software, and hardware.
Analyse results and communicate findings through technical discussions, presentations, and written reports.
Produce clear, reproducible research code and supporting documentation.

Benefits

Reimbursement of reasonable expenses incurred as part of the role, such as approved travel to meetings or conferences.
Free snacks and refreshments.
Regular social and cultural events.
Reasonable accommodations for applicants with disabilities.

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