PCB Layout Design Engineer

INFOTRON•Mountain View, CA

2d•$120,000 - $150,000•Hybrid

About The Position

We are seeking an experienced PCB Layout Design Engineer to support development of advanced, high-speed electronic systems for next-generation computing platforms. The role focuses on hands-on PCB layout design using Altium Designer, including complex routing, dense BGA designs, stack-up development, and signal integrity considerations. Experience with high-speed designs in the 1–10+ Gbps range is preferred; experience with 200 Gbps designs is not required. This is a contract position through December 2026, with potential extension or conversion to full-time based on 2027 budget approval. The position may be based in Mountain View, California, on a hybrid basis, or fully remote. Flexible work-from-home options are available.

Requirements

Strong hands-on experience with Altium Designer.
Professional experience in a dedicated PCB Layout Design role.
Experience designing and routing complex, high-speed PCBs.
Understanding of high-speed routing, impedance control, stack-up development, and dense BGA layouts.
Familiarity with PCB fabrication, assembly, and manufacturing processes.
Experience with high-speed interfaces operating in the 1–10+ Gbps range or higher.
Strong collaboration and communication skills to work effectively with cross-functional engineering teams.

Nice To Haves

Experience with CPU, GPU, server, data center, or high-performance computing hardware.
Knowledge of HDI PCB technologies and power delivery network design.
Experience partnering with Signal Integrity and Power Integrity teams.
Familiarity with PCIe, memory interfaces, and SERDES technologies.
Experience with ASIC-driven PCB development workflows and design automation.
Experience generating and reviewing ODB++, Gerber, and fabrication outputs.

Responsibilities

Design and develop high-speed PCB layouts for advanced GPU, CPU, server, and high-performance computing platforms.
Define component placement, ASIC ball-out, footprints, routing strategies, stack-ups, and design constraints.
Develop and implement layout rules for high-speed interfaces, including PCIe, memory, SERDES, and power delivery networks.
Collaborate with Signal Integrity (SI), Power Integrity (PI), mechanical, thermal, packaging, and manufacturing teams.
Perform design rule checks (DRC) and PCB verification to ensure design quality and release readiness.
Generate and review manufacturing deliverables, including ODB++, Gerber files, and fabrication documentation.
Ensure PCB designs meet electrical performance, manufacturability, and reliability requirements.
Participate in design reviews and resolve PCB layout issues throughout the development lifecycle.