PCB Design Layout Engineer

NVIDIA•Santa Clara, CA

3d•$200,000 - $322,000

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

Requirements

Hold a B.S.E.E or Computer Sciences degree (or equivalent experience) with at least 12 plus years industry experience.
Knowledge of PCB design and consideration for layout, routing, and timing constraints, DFM, DFA, and DFT constraints in volume manufacturing.
Understanding of High-Density Interconnect PCB layout and PCB Signal Integrity.
Proven ability to work with a team while taking personal responsibility for your own contributions.
Agility in changing focus as the needs of our effort evolve.
Strong leadership, communication, and presentation abilities.

Nice To Haves

Experience in high-speed PCB design.
Experience in designing PCB's in the 25gbps + range using back-drilling technology.
Building complex multi-layer HDI PCB's for very dense placement and routing.
Knowledge with Cadence Allegro PCB design tool.

Responsibilities

Working closely with product design engineers, perform PCB layout of high speed/high-density value conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive, Professional, Data Center, Deep Learning and AI), all using Cadence PCB design tools Allegro 23.1 and Capture.
Focus on the complete development of PCB layout, floor planning and detailed component placement, constraint management, with a concept of topology and signal/trace integrity.
Create designs that follow SI constraints, EMI/RFI control and FCC, UL and European regulations, IPC specifications and NRC regulations.