Packaging Design Engineer

Advanced Micro Devices, Inc•San Jose, CA

2d•Hybrid

About The Position

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE TEAM: The AECG - Embedded Team builds and optimizes platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale. THE ROLE: The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package group, you will work across chip, technology and systems teams to define cost effective and high performance solutions. THE PERSON: This is a high visibility position working on multiple package families for the FPGA devices. The ideal candidate should have the ability to understand electrical requirements and translate to the proper package technology requirements that is cost effective and manufacturable. This role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages.

Requirements

Bachelor’s or Master's degree in Engineering
Current working Knowledge of Cadence package design tool is a must.
Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc.

Nice To Haves

Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines.
Package/PCB layout experience.
Experience in high power, Gbs IO products is a plus.
knowledge of SKILL is a plus.
Knowledge on DoE, DFM/DFR is a plus.
Good knowledge of SerDes design and package/PCB layout constraints.
Mentor junior package designers in the group.

Responsibilities

Use Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off.
Use analytical and simulation tools to define package/module design requirements (technology, stack-up, etc.) in the project conception stages and negotiate with chip/system teams on product specification.
Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stack-up, manufacturing time etc) for various device packaging.
Collaborate with PCB Layout Engineers to optimize the package ballmap and chip team to optimize the die size.
Develop multi-signal package/module models over 50 GHz bandwidth and suitable test structures for model to measurement correlation.
Come up with performance metrics for organic package technologies in order to design high speed chips and systems.
Performing Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model to measurement correlation.
Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.