Package Designer

SK hynix•San Jose, CA

10d•Onsite

About The Position

SK hynix America is a global leader in HBM, DRAM, and NAND flash technologies, developing advanced memory solutions for mobile technology and AI data centers. The company is making significant investments in the U.S. and is a key player in the AI revolution, building critical digital infrastructure with a commitment to sustainable operations. They are seeking innovative minds to join their collaborative team in pioneering next-generation memory technologies and expanding their market footprint.

Requirements

Bachelor's or Master's degree in Electrical Engineering (Preferred), Mechanical Engineering, Materials Science, or a related field
3+ years of experience in semiconductor package design or layout
Proven experience with package layout tools (Cadence Allegro/Virtuoso/Innovus, Siemens Xpedition, Synopsys 3D-ICC, Autocad or equivalent)
Strong understanding of high-speed signal routing and power distribution networks (PDN)
In-depth knowledge in 2.5D/3D packaging technologies, substrate design rules, and large body substrate technologies
Effective communication skills and ability to work in a fast-paced, cross-functional environment

Nice To Haves

Currently pursuing a PhD's degree in Electrical Engineering or a related field
5+ years of experiences in advanced packaging technology development and manufacturing
Experience with SI/PI simulation tools (Ansys, HFSS, ADS)
Proven technical understanding of advanced packaging materials, their interactions, failure mechanisms and analytical techniques

Responsibilities

Design and layout of advanced semiconductor packages including Flip Chip, BGA, LGA, 2.5D/3D heterogeneous integration with High Bandwidth Memory (HBM)
Use EDA tools (Cadence Allegro/Virtuoso/Innovus, Siemens Xpedition, Synopsys 3D-ICC etc.) to create and verify package layouts
Perform Signal Integrity (SI) and Power Integrity (PI) analysis in collaboration with SI/PI engineers
Perform design and what-if scenario analysis for novel advanced packaging schemes to improve system-in-package (SIP) performance.
Create and maintain design rules, stack-ups, and layout guidelines
Collaborate with internal and external stakeholders to ensure seamless advanced packaging technology development