Package Designer

SK hynix America•San Jose, CA

11d•$110,000 - $155,000•Onsite

About The Position

At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers. With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering (Preferred), Mechanical Engineering, Materials Science, or a related field
3+ years of experience in semiconductor package design or layout
Proven experience with package layout tools (Cadence Allegro/Virtuoso/Innovus, Siemens Xpedition, Synopsys 3D-ICC, Autocad or equivalent)
Strong understanding of high-speed signal routing and power distribution networks (PDN)
In-depth knowledge in 2.5D/3D packaging technologies, substrate design rules, and large body substrate technologies
Effective communication skills and ability to work in a fast-paced, cross-functional environment

Nice To Haves

Currently pursuing a PhD's degree in Electrical Engineering or a related field
5+ years of experiences in advanced packaging technology development and manufacturing
Experience with SI/PI simulation tools (Ansys, HFSS, ADS)
Proven technical understanding of advanced packaging materials, their interactions, failure mechanisms and analytical techniques

Responsibilities

Design and layout of advanced semiconductor packages including Flip Chip, BGA, LGA, 2.5D/3D heterogeneous integration with High Bandwidth Memory (HBM)
Use EDA tools (Cadence Allegro/Virtuoso/Innovus, Siemens Xpedition, Synopsys 3D-ICC etc.) to create and verify package layouts
Perform Signal Integrity (SI) and Power Integrity (PI) analysis in collaboration with SI/PI engineers
Perform design and what-if scenario analysis for novel advanced packaging schemes to improve system-in-package (SIP) performance.
Create and maintain design rules, stack-ups, and layout guidelines
Collaborate with internal and external stakeholders to ensure seamless advanced packaging technology development