Neural Network Microarchitect

Rivian•Palo Alto, CA

About The Position

Rivian is seeking a Principal Neural Network Microarchitect to lead the definition of Rivian’s next-generation Neural Network Engine (NNE) microarchitecture. This role is aligned to Rivian’s Professional track at RIV-8 (Principal), where the expectation is broad technical expertise, ownership of critical design matters, and work that shapes future products and technologies. You will drive the architecture of the NNE core with emphasis on datapath design, scheduling, quantization-aware execution, partitioning, and performance scalability for production neural network workloads. At Rivian, the RAP1 SoC NNE includes a large processing array, configurable partitioning, instruction DMA engines, data DMA engines, and substantial on-chip SRAM, making this a deeply cross-functional architecture role spanning compute, memory movement, software interfaces, and system constraints.

Requirements

Deep expertise in computer architecture and hardware microarchitecture, with a strong track record designing complex silicon blocks from concept through production.
Strong understanding of neural network inference hardware, including datapath design, scheduling, numerical formats, quantization, and performance optimization.
Experience architecting or optimizing specialized compute engines such as NPUs, AI accelerators, vector/tensor processors, or systolic-array-based architectures.
Strong knowledge of memory hierarchy and data movement, including SRAM organization, DMA-based transfer models, buffering, bandwidth management, and latency hiding.
Experience working across hardware and software boundaries, especially with compiler, runtime, or model deployment teams.
Proven ability to evaluate architectural tradeoffs using modeling, analysis, and empirical workload characterization.
Excellent communication skills and the ability to influence across architecture, design, verification, physical design, firmware, compiler, and product teams.
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.

Nice To Haves

Experience with automotive or safety-aware silicon development.
Experience with neural network workloads such as CNNs, transformers, RNNs, or related model classes used in perception and autonomy contexts.
Familiarity with instruction-driven accelerator architectures, partitioned compute fabrics, and high-efficiency memory orchestration.
Experience defining architecture for systems that balance throughput, determinism, power efficiency, and debuggability.

Responsibilities

Define and evolve the NNE core microarchitecture, including compute datapaths, instruction flow, scheduling strategy, quantization support, and execution efficiency for neural network inference workloads.
Architect solutions that map effectively onto Rivian’s NNE hardware model, including the processing array, partitioning strategy, and coordination of instruction and data movement across the engine.
Drive architectural tradeoffs across performance, power, area, utilization, latency, and scalability.
Lead definition of mechanisms for efficient movement of activations, weights, and outputs through on-chip and off-chip memory pathways and DMA architecture.
Partner closely with compiler, model, firmware, verification, and SoC teams to ensure neural network workloads are translated into efficient executable flows for the NNE. Rivian’s compiler flow translates network descriptions into instruction streams executed on the NNE, so tight hardware-software co-design is essential.
Define architectural requirements for correctness, observability, resiliency, and debuggability, including support for error handling, recovery hooks, and safe execution flows where needed.
Build performance models, evaluate bottlenecks, and guide decisions with data across representative production workloads.
Influence long-range NNE direction, establish technical principles, and serve as a key architecture voice across the silicon organization. At the RIV-8 level, this role is expected to contribute to company objectives and use broad expertise to resolve critical issues and broad design matters.
Mentor engineers across architecture and implementation disciplines and raise the technical bar for neural network accelerator design at Rivian.