Drive the Next Wave of Computing Innovation at MIPS At MIPS, we’re shaping the future of compute architecture with advanced IP that powers a wide range of applications. We take a disciplined, methodical approach to designing scalable, energy-efficient solutions that meet demanding power, performance, and area goals. Our team spans from architecture, performance modeling, design, verification, implementation to software and software optimization for our customers. The team thrives on collaboration, technical depth, and a culture of mutual respect. We value diverse perspectives and practical experience, and we know that excellence is built through thoughtful teamwork and a commitment to the highest engineering standards. We’re seeking a seasoned CPU microarchitect who brings hands-on RTL development experience and a track record of technical leadership. We’re looking for expertise in one or more of the following areas: Instruction fetch and branch prediction, instruction decode, scheduling, Out-of-order execution, register renaming, Integer- or floating-point execution, exception handling, Load/store execution, cache design, or memory subsystems As part of our team, you’ll have the opportunity to take ownership of critical design challenges, mentor colleagues, and contribute to innovations that will define the next generation of MIPS computing solutions.
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Job Type
Full-time
Career Level
Senior
Education Level
Associate degree