ML Silicon Performance Lead

OpenAI • San Francisco, CA

2d • $287,000 - $485,000

About The Position

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for advanced AI workloads, including future generations of silicon and tightly integrated systems for its supercomputing platform. The ML Silicon Performance Lead drives hardware/software co-design across models, kernels, compilers, and silicon to determine how machine-learning workloads map to hardware and how hardware should evolve to support them. The role connects model and workload requirements with compute, memory, and specialized acceleration capabilities to improve performance, efficiency, and scalability across current and future AI silicon.

The lead partners with ML research, compiler, and silicon architecture teams to develop software approaches and hardware capabilities. They evaluate tradeoffs involving kernel mapping, quantization, data structures, and specialized IP; use performance modeling, simulation, and hands-on optimization to guide architectural decisions; and validate improvements on representative workloads.

Requirements

• Deep experience with ML accelerator architecture and how compute resources, memory systems, and data movement shape workload performance.
• Ability to translate model-level behavior into concrete kernel requirements and hardware design decisions.
• Experience building or using accelerator performance models and simulators, and validating assumptions and interpreting limitations.
• Hands-on experience optimizing ML kernels, including identifying bottlenecks and improving utilization, locality, and execution efficiency.
• Understanding of quantization and numerical formats and their implications for model quality, memory bandwidth, compute efficiency, and hardware support.
• Experience with hardware/software co-design and the ability to assess whether a capability belongs in a kernel, compiler, instruction set, or dedicated hardware.
• Ability to work effectively across research, compiler, and silicon teams, clarify ambiguous requirements, and build alignment through technical evidence.
• Candidates may need to meet certain legal-status requirements under U.S. export control laws and regulations.

Responsibilities

• Drive hardware/software co-design across ML research, compiler, and silicon teams, shaping kernel implementations and hardware capabilities to meet workload performance and efficiency goals.
• Translate model and workload needs into kernel performance targets and compute, memory-capacity, and bandwidth requirements, and relay hardware constraints and opportunities to inform model and algorithm choices.
• Map and optimize ML kernels for the architecture, using data movement, memory hierarchy, and execution-efficiency insights to guide software improvements and hardware design.
• Co-design support for new data structures and quantization formats across kernels, compilers, and silicon, balancing model quality, numerical behavior, performance, power, and implementation cost.
• Define and help develop specialized acceleration IP with compiler and silicon partners, determining the appropriate division of functionality across software, instructions, and dedicated hardware.
• Drive ML performance modeling and simulation with the compiler team to compare design options, identify bottlenecks, and quantify end-to-end benefits on representative workloads.
• Partner with the Silicon Architecture lead and silicon team to specify and validate new IP, using kernel and simulation results to refine requirements and prioritize architectural improvements.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed