Memory Packaging Engineer

Apple•Austin, CA

About The Position

The Memory Packaging Engineer will define, develop, and qualify next-generation memory packages for Apple products. The role guides memory partners’ package roadmaps and collaborates with internal engineering teams to enable bandwidth and density scaling. The engineer owns work across the product lifecycle, from initial concept through qualification, and evaluates available and emerging packaging technologies to determine next-generation package architecture. The position also involves solving electrical, mechanical, and thermal integration challenges; driving vendor design of experiments and failure analysis to improve downstream yield and quality; defining the memory package plan of record, including form factor, process, layout, stackup, and bill of materials; and driving vendors to develop materials and technologies for leading-edge package design rules.

Requirements

  • Bachelor’s degree and 10 or more years of relevant industry experience.
  • 10 or more years of industry experience in package design and assembly process development of high-bandwidth, high-density memory packages.
  • Strong knowledge of thin-die stacking technologies, including wirebond, flip-chip, and wafer/die bonding.
  • Strong knowledge of packaging materials and design to engineer warpage and CTE properties and mitigate thermal challenges.
  • Working experience in package test and reliability, system-level downstream process interaction, and packaging inspection metrology.
  • Deep understanding of signal integrity/power integrity co-design with memory die and high-speed DDR or differential signaling.
  • Understanding of how memory die floorplan and architecture influence package structure and routing, including experience collaborating with memory die design teams.
  • Excellent communication skills for collaborating with internal teams and managing external vendors.

Nice To Haves

  • Master’s or Ph.D. degree.

Responsibilities

  • Determine next-generation package architecture by evaluating available and emerging packaging technologies.
  • Collaborate with cross-functional teams to solve electrical, mechanical, and thermal integration challenges.
  • Drive vendor design of experiments and failure analysis to improve downstream yield and maintain quality and reliability.
  • Define the memory package plan of record, including package form factor, process, layout, stackup, and bill of materials.
  • Drive memory vendors to develop package materials and technology for leading-edge package design rules.
  • Guide memory partners’ package roadmaps and collaborate with internal engineering teams to enable bandwidth and density scaling.
  • Own package work across the product lifecycle, from initial concept through qualification.
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