Lead SoC Design Verification (DV) Engineer

TYLsemi•San Jose, CA

1d•$237,500 - $286,000

About The Position

We are seeking an analytical and strategic SoC Design Verification (DV) Lead to architect, drive, and execute the verification strategy for our next-generation semiconductor products. In this role, you will lead a team of verification engineers tasked with validating highly complex, multi-million gate SoC designs. You will work side-by-side with the SoC Front-End Lead and cross functional teams including Emulation and Firmware teams to establish robust methodologies and guarantee first-time-right silicon through rigorous block-level, subsystem, and full-chip verification.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
12+ years of hardware verification experience, with a proven history of tape-out success on complex, large-scale SoCs.
Master-level proficiency in SystemVerilog and UVM.
Deep expertise in constrained-random verification, functional coverage model design, and writing complex SystemVerilog Assertions (SVA).
Expert familiarity with major EDA simulator and debug platforms.
Strong analytical problem-solving skills and excellent cross-functional communication to balance verification thoroughness with strict project timelines.

Nice To Haves

Experience using Formal Verification methodologies to verify complex control logic.
Hands-on experience with hardware emulation platforms for speed-up or OS-booting.
Strong proficiency in scripting to manage continuous integration (CI/CD) and automated regression triage.

Responsibilities

Lead, mentor, and grow the verification team.
Architect the overall verification environment, defining the standards for testbenches, automation scripts, and regression metrics.
Translate architectural specifications into comprehensive verification plans.
Identify edge cases, corner cases, and critical scenarios that must be stress-tested.
Own and build modular, scalable, and reusable advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM).
Deploy AI-driven verification methodology for SoC Verification.
Deploy formal verification, assertion-based verification (SVA), and hardware/software co-verification where appropriate to accelerate bug discovery.
Manage verification at all levels—from complex customized internal blocks to standard third-party IPs and full-chip fabrics.
Ensure proper validation of critical system features like power management (UPF), clocking/resets, and security features.
Track and drive functional coverage, code coverage, and assertion metrics to absolute closure.
Define and enforce the official bug-bar and criteria for pre-silicon signoff.
Partner directly with the Front-End Design Lead to resolve complex RTL bugs.
Coordinate with Emulation and Post-Silicon validation teams to cleanly hand off test suites and debug insights.