Sr. Staff Engineer, SoC Design Verification

Tenstorrent•Boston, MA

2h•$100,000 - $500,000•Hybrid

About The Position

Tenstorrent is seeking a Sr. Staff Design Verification Engineer to lead end-to-end verification efforts for their advanced CPU and AI compute platforms. This role is for seasoned engineers with deep expertise in CPU verification who can drive complex test plans to closure, mentor teams, and leverage AI tools. The position is hybrid and based in Boston, Toronto, Ottawa, or Santa Clara. The company welcomes candidates at various experience levels, and the final level will be determined during the interview process.

Requirements

Proven track record leading end-to-end CPU verification across processor cores, caches, interconnects, interrupts, MMU/IOMMU, and cache coherency protocols.
Expert in creating comprehensive test plans and building simulation testbenches using SV-UVM, C/DPI, and Cocotb.
Skilled in managing high-volume regression execution, complex failure triage, and driving test plans and coverage metrics to closure.
Experienced leader and mentor dedicated to guiding junior engineers and fostering verification best practices across teams.
Proficient in leveraging modern AI tools like Copilot, Cursor, Claude, Gemini, and ChatGPT to optimize verification workflows.

Nice To Haves

Multi-chip and emulation experience a plus.

Responsibilities

Lead the development and execution of end-to-end DV strategies for CPU and AI accelerator blocks & chiplets, ensuring robust coverage and sign-off.
Build and maintain advanced simulation environments using SV-UVM, C/DPI, Cocotb, and other methodologies to verify complex designs.
Drive test plan ownership, including coverage analysis, regression management, triage, and closure for multi-block CPU subsystems.
Collaborate with design, architecture, post silicon and software teams to review plans and debug issues.
Mentor junior DV engineers, sharing expertise in verification flows and leveraging AI-assisted tools; support emulation and multi-chip verification flows where applicable, optimizing for scalability and efficiency.