Electrical Engineering - Cleared Contractor - L5
About The Position
The Senior Member of Engineering Staff (SMES) will be part of the key design team responsible for delivering FPGAs for defense applications. Reporting to the Manager, Engineering (ASIC/FPGA), this role architects and implements FPGA designs, with hands-on design and debugging focused primarily on Ethernet, I2C, SPI, and AXI protocols. The position supports communication products for National Security and contributes to robust quality and delivery. The organization uses EDA flows and methodologies including Mentor EDA tools and verification methods, Synopsys tools, and Xilinx, Intel, and Microchip FPGA tools. It also supports targeting multiple FPGA vendors and ASIC front-end design. The role includes FPGA specification, architecture, RTL implementation and simulation, synthesis and timing analysis, design-quality checks, verification, hardware bring-up, integration testing, and product collateral supporting NSA certification.
Requirements
- Bachelor of Science, master's, or PhD from an accredited course of study in engineering, engineering technology, or a listed related field; the posting also lists an associate degree as the minimum education required.
- 5–7+ years of experience designing FPGA products with VHDL.
- Experience with Xilinx FPGAs and Vivado.
- Experience with a revision control system.
- Experience with Earned Value Management (EVM).
- Good written, verbal, and presentation skills.
- Active DoD Secret security clearance.
Nice To Haves
- Experience mapping algorithms to architecture.
- Experience in C++ and object-oriented programming.
- Experience with one or more of Ethernet, TCP/IP, PCIe, NVMe, or USB protocols.
- Experience with Xilinx SoC design using SDKs and PetaLinux OS.
- Experience with High-Level Synthesis (HLS) using Vivado HLX or Mentor Catapult.
Responsibilities
- Derive FPGA design specifications from system requirements.
- Develop detailed FPGA architecture for implementation.
- Implement designs in RTL using VHDL and perform module-level simulations.
- Perform synthesis, place and route (PAR), and static timing analysis (STA).
- Assess RTL quality using lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), and static formal EDA.
- Generate verification test plans and perform end-to-end simulations.
- Support board and FPGA bring-up.
- Validate designs through hardware/software integration testing with test equipment.
- Support product collateral for NSA certification.
- Perform hands-on FPGA design and debugging, primarily involving Ethernet, I2C, SPI, and AXI protocols.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
