Lead FPGA Design Engineer

Neurophos • Austin, TX

1d • Onsite

About The Position

Neurophos is seeking an experienced and adaptable FPGA Development Lead to join their foundational silicon team. This role will serve as the architect of the hardware emulation and validation strategy, bridging RTL design and physical silicon. As an early team member at a rapidly evolving ASIC startup, responsibilities will extend beyond coding to encompass the entire FPGA lifecycle, including selecting appropriate hardware platforms and executing complex system-level bring-up and post-silicon characterization. The company is focused on developing a new computing architecture using silicon photonics and an active, programmable metasurface for matrix multiplications at the speed of light, aiming for significantly improved energy efficiency and performance for large-scale AI inference.

Requirements

• 10+ years of industry experience
• 5+ years of experience in FPGA design and implementation, preferably within an ASIC or high-growth hardware environment.
• Expert-level proficiency in SystemVerilog for synthesis and verification.
• Deep experience with Xilinx Vivado (Synthesis, Place & Route, Timing Closure, and IP Catalog).
• Proven experience implementing and debugging PCIe interfaces, as well as SPI, UART, JTAG, and other common interfaces.
• Startup mindset: the ability to pivot quickly, work independently, and tackle ambiguous technical challenges.
• Strong hands-on experience with board-level bringup and lab debugging.

Nice To Haves

• Experience with scripting languages (Python or Tcl) for automation of FPGA builds and testing.
• Knowledge of SoC architectures and AMBA bus protocols (AXI, AHB).
• Familiarity with high-speed SERDES tuning and signal integrity concepts.

Responsibilities

• Lead the selection and procurement of FPGA prototyping platforms (e.g., HAPS, VCU118, or custom boards) tailored for pre-silicon RTL verification and software development.
• Adapt and implement complex ASIC RTL onto FPGA targets using SystemVerilog.
• Integrate a mix of in-house designs and third-party IP.
• Design and debug high-speed interfaces, with a specific focus on PCIe Gen 3/4/5 integration and validation.
• Develop FPGA-based "tester" designs to facilitate post-silicon validation, device characterization, and automated testing environments.
• Utilize ChipScope/Vivado Analyzer and external lab equipment (oscilloscopes, logic analyzers) to solve complex timing and functional issues in a real-time environment.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching.
• Stock option opportunities.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits: Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed