FPGA Design Engineer

Booz Allen Hamilton•El Segundo, CA

3d•$69,400 - $158,000

About The Position

FPGA Design Engineer The Opportunity: We are seeking an experienced FPGA Design Engineer to support the development, optimization, and deployment of digital signal processing (DSP) functions on FPGA platforms. As a member of our engineering team, you will be responsible for designing, implementing, and validating high-performance digital systems that efficiently translate complex algorithms into synthesizable hardware for RF applications. This role involves contributing to advanced DSP workflows, enhancing real-time processing capabilities, and advancing our algorithm-to-hardware development pipeline. You will work both independently and collaboratively with multidisciplinary teams, leveraging your technical expertise to address complex challenges with minimal supervision and providing mentorship as appropriate. Our research and development environment prioritizes innovation, rapid prototyping, and problem-solving through direct hands‑on application of concepts. This position offers the opportunity to engage directly with FPGA and RF technologies and deliver impactful operational solutions. We invite you to join us in advancing our FPGA-enabled DSP and RF processing solutions.

Requirements

3+ years of experience developing FPGA or SDR solutions for DSP or RF applications, including prototyping DSP algorithms in hardware such as filtering, detection, synchronization, modulation, demodulation, transforms, and feature extraction
Experience designing FPGA solutions using Verilog, VHDL, SystemVerilog, or HLS and working with Xilinx, Vitis, or Vivado development ecosystems
Experience applying FPGA toolchain workflows, including simulation, synthesis, fitting, timing analysis, implementation, and hardware debug
Experience integrating FPGA designs with embedded hardware systems or FPGA‑connected RF front ends and adapting vendor RF transceiver reference designs, such as RTL, IP cores, or drivers, to evaluation boards or custom platforms
Experience using Python, C++, or MATLAB for modeling DSP algorithms, as well as scripting with Python, Bash, or Tcl for automation workflows
Knowledge of embedded systems concepts, including memory interfaces, buses, soft‑core CPUs, and high‑speed digital interfaces such as AXI‑Stream, AXI‑Lite, DMA, and custom streaming buses
Knowledge of Linux or UNIX development environments and digital design fundamentals, including streaming architectures, pipelining, buffering, and DataPath timing
Ability to read hardware schematics, operate lab equipment including logic analyzers, oscilloscopes, and spectrum analyzers, and collaborate in multidisciplinary teams while also working independently on complex engineering tasks
TS/SCI clearance
Bachelor’s degree in Electrical Engineering or Computer Engineering

Nice To Haves

Experience building DSP IP libraries for reuse across modem or signal‑processing applications
Experience with SystemVerilog or UVM for verification
Experience developing HLS‑friendly algorithms and optimizing C/C++ code for hardware translation
Experience with C/C++ or Rust for embedded or performance‑critical firmware
Experience with GPU acceleration, parallel computing, or high‑bandwidth data processing
Experience gathering requirements, shaping development roadmaps, or supporting Agile workflows
Knowledge of modern agentic engineering workflows, such as AI‑driven automation for FPGA design, simulation, synthesis, or testing
Master's degree in Electrical Engineering, Computer Engineering, or related field

Responsibilities

Design and implement FPGA‑based DSP systems using, HDL, Vitis HLS and modern FPGA toolchains
Develop, optimize, implement DSP algorithms, including filtering, detection, synchronization, modulation and demodulation, transforms, and feature‑extraction into high‑throughput, resource‑efficient hardware blocks.
Collaborate with cross‑functional teams to integrate FPGA designs with software, firmware, and larger system architectures
Test, verify, and validate FPGA designs, ensuring functional correctness, stability, and performance under real‑time constraints
Optimize designs for timing, area, power, and throughput using HLS directives and traditional FPGA workflows
Develop reusable hardware IP blocks, enabling scalable DSP pipelines and accelerating future development
Maintain documentation, including design notes, block diagrams, interface definitions, user guides, and workflow references
Contribute to innovation, identifying new techniques and technologies that improve FPGA development efficiency, DSP performance, or overall system capability