Lead EDA Software Engineer (C++, Characterization)

Cadence Design Systems•San Jose, CA

8d•$119,000 - $221,000

About The Position

Cadence is seeking a Lead EDA Software Engineer to join its R&D team developing technologies and products for static and dynamic transistor-level analysis of advanced custom digital and mixed-signal circuits. These tools support the communication, IoT, and AI markets. The role focuses on expanding existing tool architecture for timing analysis, creating frameworks to analyze effects dominant at n5 and below, and applying machine learning to improve speed, capacity, and usability.

Requirements

At least 5 years of experience developing EDA tools, with expertise in one or more areas: transistor-level timing, power, noise, aging, reliability, or EMIR analysis.
Strong C++ knowledge, particularly in a Linux environment.
Proficiency in designing data structures and algorithms and applying software engineering principles.
Industry experience developing and maintaining C++ applications on Unix or Linux platforms.
Experience with quality and software processes.
Ability to analyze transistor- or gate-level schematics.

Nice To Haves

A BS degree in Computer Science, Electrical Engineering, or Computer Engineering.
Experience developing circuit simulation or library characterization programs.
High-level understanding of SPICE simulation transistor models.
Experience with distributed programming, database design, and cloud APIs for distributed computing.

Responsibilities

Enhance and expand existing tools' architecture to cover timing analysis.
Create new frameworks for analyzing effects dominant at n5 and below.
Leverage machine learning technology to improve speed, capacity, and usability over existing solutions.