Lead DFT Engineer

EnCharge AI • Canada, KY

22h • $200,000 - $250,000 • Onsite

About The Position

Developing silicon for edge-to-cloud computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.

Requirements

• 12+ years in DFT, with at least 2 years in a leadership or principal role.
• Bachelor’s degree in a related field.
• Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, Cadence Modus).
• Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).
• Proven track record with FinFET nodes (7nm, 5nm, or below).
• Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.

Responsibilities

• Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.
• Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
• Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.
• Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.
• Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior