Layout Engineer (7752)
About The Position
Coordinate the design changes, design fitting issues, and other technical data to ensure customers’ designs can fit TSMC’s production flow and procedures. Specific tasks include but are not limited to: Acting as liaison between customer and TSMC fab manufacturing staff; providing training and on-site support to TSMC’s U.S. customers of TSMC specific advanced processing DDRIO/SerDes/RF layout, utilizing knowledge of TSMC’s design rules; Implementing blocks of customer’s chip, covering floor plan, timing and noise closure and power planning. Provided DDRIO/SerDes/RF block layout floorplan and layout guideline.
Requirements
- Master’s degree or foreign equivalent in Electrical Engineering, Photonics and Optoelectronics, or a related field of study
- Two (2) years of experience in a related position
- Knowledge of chip implementation technology and semiconductor fabrication processes and procedures
- Knowledge in DDR IO layout skills, mixed-mode electronic circuits, and semiconductor device expertise
- Knowledge of layout tools such as VIRTUOSO
- Knowledge of verification tools like Calibre
Responsibilities
- Acting as liaison between customer and TSMC fab manufacturing staff
- Providing training and on-site support to TSMC’s U.S. customers of TSMC specific advanced processing DDRIO/SerDes/RF layout, utilizing knowledge of TSMC’s design rules
- Implementing blocks of customer’s chip, covering floor plan, timing and noise closure and power planning
- Provided DDRIO/SerDes/RF block layout floorplan and layout guideline
Benefits
- market competitive pay
- allowances
- bonuses
- comprehensive benefits
- extensive development opportunities and programs
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
