Layout Design Intern (Summer 2026)

Ciena • Ottawa, ON

5d

About The Position

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. The WaveLogic™ family of products is a cornerstone of Ciena’s optical fiber transmission solutions and a key contributor to the company’s leadership in the global telecommunications industry. This opportunity offers hands‑on exposure to advanced high‑speed analog and mixed‑signal circuit design within a team that has shaped more than three decades of innovation in broadband fiber‑optic modems. The team pioneered the world’s first high‑speed digital‑to‑analog converter (DAC) and analog‑to‑digital converter (ADC) analog macros, enabling the evolution of coherent fiber‑optic product solutions. This co‑op role provides the opportunity to contribute directly to next‑generation high‑speed circuit development while learning from experienced engineers in a collaborative, high‑performance environment.

Requirements

• Currently pursuing a degree in Electrical Engineering or a related field
• Hands‑on experience with custom analog and mixed‑signal layout design in deep sub‑micron complementary metal‑oxide semiconductor (CMOS) technologies
• Strong understanding of layout techniques, including floorplanning, device matching, parasitic minimization, shielding, electromigration, and IR drop considerations
• Experience creating custom layouts for analog or mixed‑signal blocks such as operational amplifiers or current mirrors
• Familiarity with semiconductor manufacturing processes and foundry design rules
• Experience using industry‑standard layout tools such as Cadence Virtuoso and Siemens Calibre
• Ability to interpret and debug DRC and LVS reports effectively

Nice To Haves

• Exposure to high‑speed data converter or phase‑locked loop (PLL) layout design
• Familiarity with bipolar CMOS (BiCMOS) technologies
• Scripting experience using PERL or SKILL to support layout automation or productivity improvements
• Experience collaborating in cross‑functional hardware design teams
• Strong analytical skills with the ability to proactively identify layout‑sensitive circuit structures

Responsibilities

• Contribute to layout feasibility studies in partnership with senior analog designers, evaluating design trade‑offs and layout strategies for high‑speed circuits
• Develop custom layouts for advanced analog and mixed‑signal blocks, following structured methodologies for floorplanning, placement, and routing
• Execute comprehensive physical verification, including design rule checks (DRC), layout versus schematic (LVS), electromigration (EM), and infrared (IR) drop analysis to ensure layout quality and reliability
• Support continuous improvement by exploring new layout tool features, flows, and processes to enhance efficiency and productivity
• Collaborate closely with circuit designers and layout engineers to identify and resolve layout‑related risks early in the design cycle
• Provide clear status updates and actively participate in team meetings, design discussions, and knowledge‑sharing activities

Benefits

• Employee Assistance Program (EAP)
• company-paid holidays
• paid sick leave
• vacation pay

What This Job Offers

• Job Type: Full-time
• Career Level: Intern
• Education Level: Associate degree