IP Logic Design Engineer

Intel Corporation•Santa Clara, CA

2d•$105,650 - $172,860•Hybrid

About The Position

As an IP Logic Design Engineer, you will play a pivotal role in driving next-generation semiconductor innovation. In this role, you will develop and optimize cutting-edge IP logic designs, contributing directly to Intel's mission to shape the future of computing. Your work will impact Intel's success by delivering high-quality IP blocks and subsystems for seamless integration into full-chip designs, enabling superior power, performance, and efficiency in Intel's products. Collaborating alongside a team of world-class engineers, you will have the opportunity to influence design architecture, tackle meaningful challenges, and shape the future of semiconductor technology.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
0 to 1 or more years of experience with a Bachelor's degree, or 0 years of experience with a Master's degree.
Proficiency in RTL design and development using System Verilog and Verilog.
Hands-on experience with clock design, clock gating, and clock domain crossing.
Experience with UPF low-power coding and debugging techniques.
Familiarity with problem-solving approaches for power, performance, area, and timing optimization.

Nice To Haves

Master's degree in Electrical Engineering, Computer Engineering, or related field.
Understanding of microarchitecture design principles and strategies.
Strong technical collaboration skills to work effectively in a team environment.
Demonstrated ability to adapt to evolving technologies and industry trends.

Responsibilities

Develop logic design and register transfer level (RTL) coding for IP blocks using languages such as System Verilog and Verilog.
Optimize logic designs to meet power, performance, area, and timing goals.
Participate in defining architecture and microarchitecture features for IP blocks.
Collaborate with cross-functional teams to review verification plans, ensuring comprehensive validation of design features.
Identify and resolve failures in RTL tests, implementing corrective measures to ensure design correctness.
Apply power-saving techniques such as clock gating and power gating to enhance energy efficiency.
Support System-on-Chip (SoC) customers with the integration and verification of IP blocks, ensuring high-quality handoff and smooth execution.
Use industry-standard tools and methodologies to ensure design integrity and compliance with quality assurance standards.