SoC IP and System Applications

TYLsemi • San Jose, CA

9d

About The Position

TylSemi is looking for an IP and Systems Application Engineer who can sit at the intersection of silicon, IP, and customer success. This role will own the operational thread that connects strategic initiatives to customers, ensuring every engagement moves with precision from idea to silicon. This is a high-visibility, high-ownership role at a company in its earliest and most consequential stage. The engineer will work directly with founders, customers, and leading semiconductor ecosystem players, with no layers and no ambiguity about impact.

Requirements

• 15+ years of technical customer management experience in semiconductor, custom silicon, or chiplet/advanced packaging environments
• Experience interfacing with ecosystem partners — chip development schedules, interdependencies on EDA and IP, tape-out schedules and system bringup timelines
• Familiarity with silicon fabrication, advanced packaging formats: CoWoS, InFO, 2.5D/3D integration, substrate/interposer-based assembly
• Technical fluency in SoC or chiplet design flows — enough to understand RTL milestones, DV sign-off, PD handoffs, and silicon bring-up phases without needing translation
• Strong communication skills — comfortable presenting program status and risk posture to internal and external stakeholders
• Proficiency with program tracking tools (and spreadsheet-based trackers); experience building program infrastructure from scratch is a plus

Nice To Haves

• Prior experience at an IP company, chiplet startup, merchant silicon company, or systems company
• Background in AI/ML infrastructure silicon — accelerators, network switches, CPO-enabled platforms
• Exposure to EDA infrastructure programs (SNPS/CDNS cloud flows)
• Familiarity with key connectivity IPs UCIe, PCIe Gen 5/6/7+, or high-bandwidth D2D interconnect standards is a strong plus

Responsibilities

• Manage active customer engagements: from IP and SoC architectural spec alignment through silicon and systems bringup and volume shipment milestones
• Ensure alignment with internal engineering and ecosystem partners — including foundries, OSAT/packaging houses, EDA vendors (Synopsys, Cadence), and IP partners
• Translate customer requirements (silicon architecture, interface specs, package form factor, delivery schedules) into internal program plans with clear owners and dates
• Build and maintain trackers, risk registers, and executive dashboards covering each engagement
• Drive gate reviews and weekly program syncs across internal RTL/DV, physical design, and validation teams
• Manage internal and external scoping and delivery timelines in coordination with technical and business teams
• Identify and escalate risks early; propose and implement mitigations before they become schedule threats

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed