Interconnect Micro-architect/RTL Design Engineer

Advanced Micro Devices, Inc•Austin, TX

52d•Hybrid

About The Position

As a member of the Infinity Fabric Architecture and RTL team, you will design and implement key components of a scalable, coherent on-chip network that enables high-speed communication across CPUs, GPUs, and accelerators. This role focuses on defining microarchitecture and developing RTL for interconnect (NoC/fabric) subsystems that support a wide range of products including servers, AI platforms, client devices, and gaming systems. You will work closely with cross-functional teams across Austin and global sites to deliver high-quality, performance-optimized hardware in a collaborative, fast-paced environment.

Requirements

Experience with RTL design using Verilog or SystemVerilog
Background in interconnect, network-on-chip (NoC), or cache/memory subsystem design
Understanding of processor architecture, including coherency and memory systems
Knowledge of digital design fundamentals and high-speed hardware systems
Experience debugging RTL or hardware systems
Familiarity with power, performance, and area tradeoffs
Exposure to scripting or programming languages such as Python, C, or C++
Awareness of design-for-test (DFT) concepts
Familiarity with x86 or ARM architectures is helpful
Interest in using AI-assisted tools to improve design and debugging workflows
BS, MS, or PhD degree in Electrical or Computer engineering preferred.

Responsibilities

Define microarchitecture for interconnect (fabric / network-on-chip) components
Develop and implement synthesizable RTL using Verilog/SystemVerilog
Optimize designs to meet power, performance, area, and timing goals
Contribute to scalable, coherent interconnect solutions across multiple product lines
Collaborate with architecture, verification, and cross-functional engineering teams
Support unit-level validation and deliver high-quality RTL to verification teams
Develop assertions and contribute to coverage strategies
Debug design issues during pre-silicon and post-silicon phases
Create clear and maintainable design documentation