Integration RTL Design Engineer

Advanced Micro Devices, Inc•San Jose, CA

88d•Hybrid

About The Position

Join AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.

Requirements

Proven expertise across the entire chip development lifecycle—from RTL design through silicon bring-up.
Excel in Verilog RTL coding, timing closure, and physical design awareness.
Multiple production tape-outs under your belt.
Deep technical expertise, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.

Nice To Haves

Proven track record with 2+ production ASIC tape-outs in senior design roles
Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices
Hands-on experience with the complete ASIC design flow: RTL → Synthesis → STA → Physical Design → Tape-out
Experience writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints
Experience integrating complex IP blocks into SOC designs
Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB)
Knowledge of ARM architecture and AMBA protocol specifications
Experience with low-power design techniques (clock gating, power gating, voltage scaling)
Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting
Exposure to formal verification tools for equivalence checking and property verification
Familiarity with AI-assisted design tools and modern EDA technologies
Experience mentoring junior engineers and leading design teams
Strong technical writing skills for design specifications and documentation
Excellent communication and collaboration skills in cross-functional environments

Responsibilities

Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing closure.
Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with industry-standard protocols (AMBA AXI/AHB/APB, PCIe, CXL).
Partner with verification teams to ensure comprehensive functional coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality reviews and signoff.
Work closely with physical design engineers on floorplanning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence and manufacturing readiness.
Develop Python/Perl/Tcl scripts to automate repetitive tasks, improve design quality checks, and enhance team efficiency throughout the design flow.
Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges and deliver high-quality silicon on schedule.