About The Position

Le groupe Timing and Communication (TCG) de Microchip recherche activement un ingénieur principal en conception analogique. Les responsabilités couvrent un large éventail d’activités telles que la conception, la simulation et la validation de circuits intégrés analogiques (CI). Les produits sont généralement des conceptions SoC à signaux mixtes. L’équipe analogique développe les blocs IP critiques utilisés dans les produits de synchronisation du TCG. Ces circuits comprennent des PLL multi-GHz, des circuits numériques haute vitesse, des pilotes MEMS ainsi que des pads d’E/S à hautes performances et haute vitesse. As an Analog Design Engineer and a member of the Analog IP team, you will: • Work with analog design leads and architects to design specific analog IP blocks. • Simulate analog circuits across process corners and operating conditions. • Develop models of design blocks for inclusion in top-level mixed-signal simulations. • Perform block-level validation of silicon process devices and system-level laboratory evaluation.

Requirements

  • Master’s degree or PhD in electrical engineering
  • Minimum 5 years of direct experience working on analog and mixed-signal circuits.
  • High-speed and analog circuit design experience including the following: ADCs, DACs, Filters, PLLs, DLLs, and high-speed I/Os.
  • Strong fundamentals in circuit theory, design, and layout
  • Hands-on experience in scripting and automation using skill language, python, Perl and tcl
  • Strong knowledge in Cadence IC design flow and tools
  • Strong knowledgeable in Verilog-A for analog behavioral modeling and simulation

Nice To Haves

  • Expertise in the system design of mixed signal circuits is preferred
  • Good communication, teamwork skills and experience working with multi-site teams are desirable

Responsibilities

  • Work with analog design leads and architects to design specific analog IP blocks.
  • Simulate analog circuits across process corners and operating conditions.
  • Develop models of design blocks for inclusion in top-level mixed-signal simulations.
  • Perform block-level validation of silicon process devices and system-level laboratory evaluation.
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